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core10100 v4.0 handbook
actel corporation, mountain view, ca 94043 ? 2009 actel corporation . all rights reserved. printed in the united states of america part number: 50200077-6 release: february 2009 no part of this document may be copied or reproduced in any form or by any means without prior written consent of actel. actel makes no warranties with respect to this do cumentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. information in this document is subject to change without notice. actel assumes no responsibility for any errors that may appear in this document. this document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of actel corporation. trademarks actel and the actel logo are registered trademarks of actel corporation. adobe and acrobat reader are registered trademarks of adobe systems, inc. all other products or brand names mentioned are tradem arks or registered trademarks of their respective holders.
v4.0 3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 supported device families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 core versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 supported interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 device utilization and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 memory requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 functional block descript ions . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 importing into libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 simulation flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 synthesis in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 interface descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 parameters on core10100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 parameters on core10100_ahbapb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ahb/apb interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 frame data and descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 internal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 core10100csr interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 core10100data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 core10100_ahbapbapb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 core10100_ahbapbahb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 core10100-rmii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 clock and reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6 testbench operation and modification . . . . . . . . . . . . . . . . . . . . . . 71 user testbench (core10100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ahbapb user testbench (core10100_ahbapb) . . . . . . . . . . . . . . . . . . . . . . . . 72 7 system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 usage with cortex?-m1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 a user testbench support routines . . . . . . . . . . . . . . . . . . . . . . . . . 75
table of contents core10100 v4.0 4v4.0 vhdl support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 verilog support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 b transmit and receive functional timi ng examples . . . . . . . . . . . . . . . 87 transmit examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 receive examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 c list of document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 d product support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 actel customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 contacting the customer technical support center . . . . . . . . . . . . . . . . . . . . . . . 101 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
v4.0 5 introduction core10100 is a high-speed media access control (mac) ethernet controller ( figure 1 ). it implements carrier sense multiple access with collision detection (csma/cd) algori thms defined by ieee 802.3 for mac over an ethernet connection. communication with an external host is implemented via a se t of control and status registers and the dma controller for external shared ram. for data transf ers, core10100 operates as a dma master. it automatically fetches from transmit data buffers and stores receive data buffers into external ram with minimum cpu intervention. linked list management enables the use of various memory a llocation schemes. internal rams are used as configurable fifo memory blocks, and there are separate memory blocks fo r transmit and receive processes. the core has a generic host-side interface that connects with external cpus. this host interface can be configured to work with 8-, 16-, or 32-bit data bus widths with big- or little-endian byte ordering. figure 1 core10100 block diagram figure 2 shows a typical application using core10100. typical appl ications include lan controllers, afdx controllers, and embedded systems. figure 1-1 on page 11 shows the primary blocks of core10100. figure 2 typical core10100 application transmit data ram data interface control interface transmit control receive data ram transmit rmii/mii receive rmii/mii control and status registers and control logic address ram data controller receive control shared ram cpu (8-, 16-, or 32-bit) data interface bus control interface bus rmii/mii interface phy core10100
introduction core10100 v4.0 6v4.0 figure 3 shows an arm?-based system using core10100_ahbapb. this system can be automatically created in smartdesign. figure 3 arm-based syste m using core10100_ahbapb
core10100 v4.0 supported device families v4.0 7 supported device families igloo? iglooe proasic3 proasic3e proasic?3l fusion proasic plus ? axcelerator? rtax-s core versions this handbook applies to core10100 and core10100_ahb v4.0. the release notes provided with the core list known discrepancies between this handbook and the core release associated with the release notes. supported interfaces core10100 is available with the following interfaces: ? core10100synchronous cpu and memory interfaces (legacy interface) ? core10100_ahbapbapb slave cpu interface and ahb master memory interface actel recommends that new designs using the smartdes ign environment use the core10100_ahbapb version of the core. core10100 is provided for backwards comp liance to previous versions of core10100. the above interfaces are described in interface descriptions on page 19 . device utilization and performance core10100 can be implemented in the following actel fpga devices. table 1 through table 6 on page 9 provide the typical utilization and performance data for the core implemented in these devices. table 1 core10100 device utilization and performance for an 8-bit datapath family cells or tiles ram utilization performance (mhz) combinatorial sequential total device total igloo?/e 4,330 1,918 6,248 14 agle600 45% 30 proasic?3 proasic3e proasic3l 4,173 1,923 6,096 14 a3p6000 44% 49 fusion 4,215 1,918 6,133 14 afs600 44% 56 proasic plus ? 5,547 1,958 7,505 29 apa600 35% 27 axcelerator? 3,087 2,207 5,114 13 ax1000 28% 73 rtax-s 3,055 2,014 5,069 13 rtax1000s 28% 57
introduction core10100 v4.0 8v4.0 table 2 core10100 device utilization and performance for a 16-bit datapath family cells or tiles ram utilization performance (mhz) combinatorial sequential total device total igloo/e 4,715 2,045 6,760 14 agle600 49% 30 proasic3 proasic3e proasic3l 4,529 2,050 6,579 14 a3p600 49% 37 fusion 4,693 2,043 6,736 14 afs600 49% 36 proasic plus 6,163 2,087 8,250 29 apa600 38% 26 axcelerator 3,328 2,170 5,498 13 ax1000 30% 67 rtax-s 3,316 2,153 5,469 13 rtax1000s 30% 49 table 3 core10100 device utilization and performance for a 32-bit datapath family cells or tiles ram utilization performance (mhz) combinatorial sequential total device total igloo/e 4,715 1,963 6,678 14 agle600 48% 30 proasic3 proasic3e proasic3l 4,435 1,967 6,402 14 a3p600 46% 36 fusion 4,597 1,961 6,558 14 afs600 47% 36 proasic plus 5,938 1,997 7,935 29 apa600 65% 26 axcelerator 3,216 2,090 5,306 13 ax1000 29% 55 rtax-s 3,225 2,089 5,314 13 rtax1000s 29% 44 table 4 core10100_ahbapb device utilizat ion and performance fo r an 8-bit datapath family cells or tiles ram utilization performance (mhz) combinatorial sequential total device total igloo/e 4,408 1,936 6,344 14 agle600 46% 30 proasic3 proasic3e proasic3l 4,234 1,941 6,175 14 a3p600 45% 54 fusion 4,306 1,939 6,245 14 afs600 45% 54 proasic plus 5,656 1,975 7,660 29 apa600 35% 32 axcelerator 2,974 2,049 5,023 13 ax1000 28% 65 rtax-s 2,946 2,041 4,987 13 rtax1000s 27% 46
core10100 v4.0 device utilization and performance v4.0 9 note: data in the above tables was achieved using actel libero? integrated design environment (ide), using the parameter settings given in table 7 on page 10 . performance is for std. speed grade parts, was achieved using the core10100 macro alone, and represents the system clock (clkdma/hclk) frequency. the clkr and clkt clock domains are capable of operating at 25 mhz or 2.5 mhz, depending on the link speed. the clkcsr/ pclk clock domain is capable of op erating in excess of clkdma/hclk. table 5 core10100_ahbapb device utilizat ion and performance for a 16-bit datapath family cells or tiles ram utilization performance (mhz) combinatorial sequential total device total igloo/e 4,749 2,067 6,816 14 agle600 49% 30 proasic3 proasic3e proasic3l 4,579 2,065 6,644 14 a3p600 48% 36 fusion 4,620 2.065 6,685 14 afs600 48% 46 proasic plus 6,219 2,106 8,354 29 apa600 39% 25 axcelerator 3,054 2,166 5,220 13 ax1000 29% 65 rtax-s 3,036 2,161 5,197 13 rtax1000s 28% 43 table 6 core10100_ahbapb device utilizat ion and performance for a 32-bit datapath family cells or tiles ram utilization performance (mhz) combinatorial sequential total device total igloo/e 5,231 2,199 7,430 14 agle600 54% 30 proasic3 proasic3e proasic3l 5,011 2,197 7,208 14 a3p600 53% 35 fusion 5,169 2,195 7,364 14 afs600 53% 35 proasic plus 6,625 2,243 8,897 29 apa600 41% 25 axcelerator 3,340 2,348 5,688 13 ax1000 31% 56 rtax-s 3,380 2,359 5,739 13 rtax1000s 32% 45
introduction core10100 v4.0 10 v4.0 memory requirements core10100 uses fpga memory blocks. the actual number of memory blocks varies based on the parameter settings. the approximate number of ram blocks is given by eq 1 and eq 2 . igloo/e, proasic3/e, proasic3l, fusion, axcelerator, and rtax-s nrams = (dw / 8 (2 tfifodepth / 512 + 2 rfifodepth / 512) + addrfilter eq 1 where dw is datawidth or ahb_dwidth. proasic plus nrams = (dw / 8 (2 tfifodepth / 256 + 2 rfifodepth / 256) + 2 addrfilter eq 2 where dw is datawidth or ahb_dwidth. the number of ram blocks may vary slightly from the abov e equations due to the synthesis tool selecting different aspect ratios and inferring memories for internal logic. table 7 parameter settings parameter core10100 core10100_ahbapb 8-bit 16-bit 32-bit 8-bit 16-bit 32-bit endianess 0 0 0 1 1 1 addrfilter 11 1000 fullduplex 00 0000 csrwidth apb_dwidth 816 32 8 16 32 datawidth ahb_dwidth 816 32 8 16 32 datadepth ahb_awidth 20 24 32 20 24 32 tfifodepth 11 10 9 11 10 9 rfifodepth 12 11 10 12 11 10 tcdepth 1 1 1 1 1 1 rcdepth 2 2 2 2 2 2 rmii 11 1111
v4.0 11 1 functional block descriptions core10100 architecture, shown in figure 1-1 , consists of the functional blocks described in this section. figure 1-1 core 10100 architecture transmit data ram rlsm dma tc clkdma data interface csr interface bd rc tlsm tfifo rfifo receive data ram clkr clkt transmit rmii/mii receive rmii/mii csr (control and status registers and control logic) int rstc rst clkcsr tps rps address ram mii managment interface serial rom interface external address filtering interface mii to rmii (optional)
functional block descriptions core10100 v4.0 12 v4.0 figure 1-2 core10100_ahbapb architecture ahb ? ahb interface the ahb block implements an ahb master function, allowi ng the dma controller to access memory on the ahb bus. apb ? apb interface this apb block implements an apb slave interface, allowing the cpu to access the csr registers set. ahb interface apb interface transmit data ram rlsm dma tc bd rc tlsm tfifo rfifo receive data ram clkr clkt transmit rmii/mii receive rmii/mii csr (control and status registers and control logic) rstc tps rps address ram mii managment interface serial rom interface external address filtering interface apb ahb mii to rmii (optional)
core10100 v4.0 v4.0 13 csr ? control/status register logic the csr component is used to control core10100 operation by the host. it implements the csr register set and the interrupt controller. it also provides a generic host interface supporting 8-, 16-, an d 32-bit transfer. the csr component operates synchronously with the clkcsr clock from the host csr interface. the csr also provides a serial rom interface and mii management interface. the host can access these two interfaces via read/write csr registers. dma ? direct memory access controller the direct memory access controller implements the host da ta interface. it services both the receive and transmit channels. the tlsm and tfifo have ac cess to one dma channel. the rlsm and rfifo have access to the other dma channel. the direct memory access controller operates synchronously with the clkdma clock from the host data interface. tlsm ? transmit linked list state machine the transmit linked list state machine implements the de scriptor/buffer architecture of core10100. it manages the transmit descriptor list and fetches the data prepared for tr ansmission from the data buffers into the transmit fifo. the transmit linked list state machine controller operates sy nchronously with the clkdma clock from the host data interface. tfifo ? transmit fifo the transmit fifo is used for buffering data prepared for transmission by core10100. it provides an interface for the external transmit data ram working as fifo memory. it fetches the transmit data from the host via the dma interface. the fifo size can be configured via the co re parameters. the transmit fifo controller operates synchronously with the clkdma clock from the host data interface. tc ? transmit controller the transmit controller implements the 802.3 transmit operation. from the network side, it uses the standard 802.3 mii interface for an external phy device. the tc unit reads tran smit data from the external transmit data ram, formats the frame, and transmits the framed data via the mii. the transmit controller operates synchronously with the clkt clock from the mii interface. bd ? backoff/deferring the backoff/deferring controller implements the 802.3 half-duplex operation. it monitors the status of the ethernet bus and decides whether to perform a transmit or backoff/deferring of the data via the mii. it operates synchronously with the clkt clock from the mii interface. rlsm ? receive linked list state machine the receive linked list state machine implements the descript or/buffer architecture of core10100. it manages the receive descriptor list and moves the data from the receive fifo into the data buffers. the receive linked list state machine controller operates synchronously with the clkdma clock from the host data interface. rfifo ? receive fifo the receive fifo is used for buffering data received by core10100. it provides an interface for the external ram working as fifo memory. the fifo size can be configured by the generic parameters of the core. the receive fifo controller operates synchronously with the clkdma clock from the host data interface.
functional block descriptions core10100 v4.0 14 v4.0 rc ? receive controller the receive controller implements the 802.3 receive operation. from the network side it uses the standard 802.3 mii interface for an external phy device. the rc block transfers data received from the mii to the receive data ram. it supports internal address filtering. it also supports an external address filtering interface. the receive controller operates synchronously with the clkr clock from the mii interface. rstc ? reset controller the reset controller is used to reset al l components of core10100. it generates a reset signal asynchronous to all clock domains in the design from the external reset line and software reset. memory blocks there are three internal memory blocks required for the proper operation of core10100: ? receive data ram C synchronous ram working as receive fifo ? transmit data ram C synchronous ram working as transmit fifo ? address ram C synchronous ram working as mac address memory rmii ? rmii to mii interface the reduced media independent interface (rmii) reduces the number of pins required for connecting to the phy from 16 to 8.
v4.0 15 2 tool flows licensing core10100 is licensed in two ways: obfuscated and rtl. depe nding on your license, tool flow functionality may be limited. obfuscated complete rtl code is provided for the core, enabling th e core to be instantiated with smartdesign. simulation, synthesis, and layout can be performed with actel libero? integrated design environment (ide). the rtl code for the core is obfuscated, 1 and the some of the testbench source files are not provided. they are precompiled into the compiled simulation library instead. rtl complete rtl source code is provided for the core and testbenches. 1. obfuscated means the rtl source files have had formatting and comments removed, an d all instance and net names have been re placed with random character sequences.
tool flows core10100 v4.0 16 v4.0 the core can be configured using the configur ation gui within smartdesign, as shown in figure 2-1 and figure 2-2 on page 17 . figure 2-1 core10100 configur ation within smartdesign
core10100 v4.0 importing into libero ide v4.0 17 figure 2-2 core10100_ahbapb conf iguration within smartdesign importing into libero ide core10100 is available for download to the smartdesign ip catalog, via the libero ide web repository. for information on using smartdesign to instan tiate, configure, connect, and generate cores, refer to the libero ide online help.
tool flows core10100 v4.0 18 v4.0 simulation flows to run simulations, select the user testbench within the smartdesign core10100 configurat ion gui, right-click, and select generate design (see figure 2-1 on page 16 ). when smartdesign generates the design files, it will insta ll the appropriate testbench files. to run the simulation, simply set the design root to the core10100 instantiation in the libe ro ide design hierarchy pane and click the simulation icon in the libero ide design flow window. this will invoke model sim and automatically run the simulation. synthesis in libero ide set the design root appropriately and click the synthesis icon in the libero ide. the synthesis window appears, displaying the synplicity? project. set synplicity to use the verilog 2001 standard if verilog is being used. to perform synthesis, click the run icon. timing constraints on page 70 details the recommended timing constraints that should be used during synthesis. place-and-route in libero ide having set the design route appropr iately and run synthesis, click the layout icon in libero ide to invoke designer. core10100 requires no special place-and-route settings. timing constraints on page 70 details the recommended timing constraints that should be used during layout.
v4.0 19 3 interface descriptions core10100 is available with the following interfaces: ?csr interface ?amba both core10100 and core10100_ahbapb share a common set of set signals to the backend physical layer (phy) and address filtering interface. parameters on core10100 table 3-1 details the parameters on core10100. table 3-1 core10100 parameters parameter values default va l ue description family 0 to 99 17 must be set to match the supported fpga family: 11 C axcelerator 12 C rtax-s 14 C proasic plus 15 C proasic3 16 C proasic3e 17 C fusion 20 C igloo 21 C iglooe 22 C proasic3l fullduplex 0 to 1 0 this controls the cores suppo rt of half-duplex operation. 0 C half- and full-duplex operation supported 1 C full-duplex only when set to '1', the collision and backoff logic required to support half-duplex operation is omitted, reducing the size of the core. endianess 0 to 2 1 sets the endianess of the core: 0 C programmable by software 1 C little 2 C big when set to a nonzero value, the size of the core is reduced. addrfilter 0 to 1 1 enables the internal address filter ram. 0 C internal address filter ram disabled 1 C internal address filter ram enabled datadepth 20 to 32 32 sets the width of the address bus used to interface to the system memory. datawidth 8, 16, 32 32 sets the width of the data bus used to interface to the system memory.
interface descriptions core10100 v4.0 20 v4.0 parameters on core10100_ahbapb table 3-2 details the parameters on core10100_ahbapb. csrwidth 8, 16, 32 32 sets the width of the data bus used to access the registers within the core. tcdepth 1 to 4 1 defines the maximum number of frames that can reside in the transmit fifo at one time. the maximum number of frames that reside in the tx fifo at one time is 2 tcdepth . rcdepth 1 to 4 2 defines the maximum number of frames that can reside in the receive fifo at one time. the maximum number of frames that reside in the rx fifo at one time is 2 rcdepth -1. tfifodepth 7 to 12 9 sets the size of the internal fifo used to buffer transmit data. the size is 2 tfifodepth ahb_dwidth / 8 bytes. the transmit fifo size must be greater than tcdepth times the maximum permitted frame size. rfifodepth 7 to 12 10 sets the size of the internal fifo used to buffer receive data. the size is 2 rfifodepth ahb_dwidth / 8 bytes. the receive fifo size must be greater than rcdepth times the maximum permitted frame size. rmii 0, 1 0 when set to 1, the core supports rmii interface. when set to 0, the core supports mii interface. table 3-1 core10100 parameters (continued) parameter values default va l ue description table 3-2 core10100_ahbapb parameters parameter values default value description family 0 to 99 17 must be set to match the supported fpga family. 11 C axcelerator 12 C rtax-s 14 C proasic plus 15 C proasic3 16 C proasic3e 17 C fusion 20 C igloo 21 C iglooe fullduplex 0 to 1 0 this controls the cores suppo rt of half-duplex operation. 0 C half- and full-duplex operation supported 1 C full-duplex only when set to '1', the collision and backoff logic required to support half-duplex operation is omitted, reducing the size of the core.
core10100 v4.0 parameters on core10100_ahbapb v4.0 21 endianess 0 to 2 1 sets the endianess of the core. 0 C programmable by software 1 C little 2 C big when set to nonzero, the size of the core is reduced. addrfilter 0 to 1 1 enables the internal address filter ram. 0 C internal address filter ram disabled 1 C internal address filter ram enabled ahb_awidth 20 to 32 32 sets the width of the ahb address bus used to interface to the system memory. ahb_dwidth 8, 16, 32 32 sets the width of the ahb data bus used to interface to the system memory. apb_dwidth 8, 16, 32 32 sets the width of the apb data bus used to access the registers within the core. tcdepth 1 to 4 1 defines the maximum number of frames that can reside in the transmit fifo at one time. the maximum number of frames that reside in the tx fifo at one time is 2 tcdepth . rcdepth 1 to 4 2 defines the maximum number of frames that can reside in the receive fifo at one time. the maximum number of frames that reside in the rx fifo at one time is 2 rcdepth -1. tfifodepth 7 to 12 9 sets the size of the internal fifo used to buffer transmit data. the size is 2 tfifodepth ahb_dwidth / 8 bytes. the transmit fifo size must be greater than tcdepth times the maximum permitted frame size. rfifodepth 7 to 12 10 sets the size of the internal fifo used to buffer receive data. the size is 2 rfifodepth ahb_dwidth / 8 bytes. the receive fifo size must be greater than rcdepth times the maximum permitted frame size. rmii 0, 1 0 when set to 1, the core supports rmii interface. when set to 0, the core supports mii interface. table 3-2 core10100_ahbap b parameters (continued) parameter values default value description
interface descriptions core10100 v4.0 22 v4.0 csr interface signals table 3-3 lists the signals included on the core10100 core. table 3-3 core10100 signals name type polarity description control and status register interface clkcsr in rise csr clock csrreq in high this signal is set by a host to request a data transfer on the csr interface. it can be a read or a write request, depending on the value of the csrrw signal. csrrw in high this signal indicates the type of request on the csr interface. setting csrrw indicates a read operation, and clearing it indicates a write operation. csrbe in csrwidth/8 this signal is the data byte enable to indicate which byte lanes of csrdatai or csrdatao are the valid data bytes. each bit of the csrbe controls a single byte lane. all csrbe signal combinations are allowed. csrdatai in csrwidth the write data is provided by the system on the csrdatai inputs during the write request. csraddr in 8 the csraddr receives the address of an individual csr data transaction. the meaning of csraddr depends on the csrwidth parameter. for csrwidth = 32 (32-bit interface), only the csraddr bits from 6 down to 2 are significant. the addresses are longwo rd-aligned (32-bit) in this mode. for csrwidth = 16 (16-bit interface), the csraddr bits from 6 down to 1 are significant. the addresses are word-aligned (16-bit) in this mode. for csrwidth = 8 (8-bit interface), all bits of csraddr are significant. the addresses are byte-aligned (8-bit) in this mode. csrack out high the csrack signal indicates either that valid data is present on the csrdatao outputs during a read request or that the csrdatai inputs have been sampled during a write request. the current version of core10100 has the csrack signal statically tied to logic 1core10100 responds to reads and writes immediately. csrdatao out csrwidth the csrdatao signal provides the read data in response to a read request. data interface clkdma in rise data clock dataack in high the dataack input is an acknowledge signal supplied by the host in response to the macs request. in the case of a read operation, dataack indicates valid data is on the datai input. the datai input must be stable while dataack is set. in the case of a write operation, setting dataack indicates that the host is ready to fetch the data supplied by core10100 on the datao output. regardless of the current transaction type (write or read), a data transfer occurs on every rising edge of clkdma on which both datareq and dataack are set. the dataack signal can be asserted or deasserted at any clock cycle, even in the middle of a burst transfer. datai in datawidth the read data must be provided on the datai input by the system in response to a read request.
core10100 v4.0 parameters on core10100_ahbapb v4.0 23 datareq out high this signal is set by core10100 to put a request for the data transfer on the interface. while datareq remains active, the datarw signal is stablethere is no transition on datarw. datarw out high the datarw output indicates the type of request on the data interface. when set, it indicates a read operation; when cleared, it indicates a write operation. dataeob out high the dataeob output is an end-of-burst signal used for burst transactions. when set, it indicates the last data transfer for a current burst; when cleared, it indicates that there will be more data transfers. datao out datawidth data to be written is provided by core10100 on datao during a write request. dataaddr out datadepth this signal addresses the external memory spac e for a data transaction. the meaning of the dataaddr bits depends on the datawidth parameter. for datawidth = 32 (32-bit interface), only dataaddr bits datadepthC1 down to 2 are significant. the addresses ar e longword-aligned (32-bit) in this mode. for datawidth = 16 (16-bit interface), the dataaddr bits from datadepthC1 down to 1 are significant. the addresses are word-aligned (16-bit) in this mode. for datawidth = 8 (8-bit interface), all bits of dataaddr are significant. the addresses are byte-aligned (8-bit) in this mode. table 3-3 core10100 signals (continued) name type polarity description
interface descriptions core10100 v4.0 24 v4.0 common interface signals the following signals are included on both the core10100 and core10100_ahbapb cores. table 3-4 signals included in core10100 and core10100_ahbapb name type polarity / bus size description general host interface signal rstcsr in high host-side reset int out high interrupt rsttco out high transmit side reset rstrco out high receive side reset tps out high transmit process stopped rps out high receive process stopped serial rom interface sdi in 1 serial data scs out 1 serial chip select sclk out 1 serial clock output sdo out 1 serial data output external address filtering interface match in high external address match when high, indicates that the destination address on the matchdata port is recognized by the external address-checking logic and that the current frame must be received by core10100. when low, indicates that the destination address on the matchdata port is not recognized and that the current frame should be discarded. note that the match signal should be valid only when the matchval signal is high. matchval in high external address match valid when high, indicates that the match signal is valid. matchen out high external match enable when high, indicates that the matchdata signal is valid. the matchen output should be used as an enable signal for the exte rnal address-checking logic. it is high for at least four clkr clock periods to allow for th e latency of external address-checking logic. matchdata out 48 external address match data the matchdata signal represents the 48-bit destination address of the received frame. note that the matchdata signal is valid only when the matchen signal is high. rmii/mii phy interface clkt in rise clock for transmit operation this must be a 25 mhz clock for a 100 mbps operation or a 2.5 mhz clock for a 10 mbps operation. this input is only used in mii mode . in rmii mode, this input will be grounded by smartdesign.
core10100 v4.0 parameters on core10100_ahbapb v4.0 25 clkr in rise clock for receive operation this must be a 25 mhz clock for a 100 mbps operation or a 2.5 mhz clock for a 10 mbps operation. this input is only used in mii mode . in rmii mode, this input will be grounded by smartdesign. rx_er in high receive error if rx_er is asserted during core10100 reception, the frame is received and status of the frame is updated with rx_er. the rx_er signal must be synchronous to the clkr receive clock. rx_dv in high receive data valid signal the phy device must assert rx_dv when a valid data nibble is provided on the rxd signal. the rx_dv signal must be synchr onous to the clkr receive clock. col in high collision detected this signal must be asserted by the phy when a collision is detected on the medium. it is valid only when operating in a half-duplex mode. when operating in a full-dupl ex mode, this signal is ignored by core10100. the col signal is not required to be synchronous to either clkr or clkt. the col signal is sampled internally by the clkt clock. crs in high carrier sense this signal must be asserted by the phy when either a receive or transmit medium is non-idle. the crs signal is not required to be synchronous with either clkr or clkt. mdi in 1 mii management data input the state of this signal can be checked by reading the csr9.19 bit. rxd in 4 receive data recovered and decoded by phy the rxd[0] signal is the least significant bit. the rxd bus must be synchronous to the clkr in mii mode. in rmii mode, rxd[1:0] is used and rxd[3:2] will be grounded by smartdesign. in rmii mode, rxd[1:0] is synchronous to rmii_clk. tx_en out high transmit enable when asserted, indicates valid data for the phy on the txd port. the tx_en signal is synchronous to the clkt transmit clock. txer out high transmit error the current version of core10100 has the txer signal statically tied to logic 0 (no transmit errors). mdc out rise mii management clock this signal is driven by the csr9.16 bit. mdo out 1 mii management data output this signal is driven by the csr9.18 bit. mden out high mii management buffer control table 3-4 signals incl uded in core10100 and co re10100_ahbapb (continued) name type polarity / bus size description
interface descriptions core10100 v4.0 26 v4.0 ahb/apb interface signals table 3-5 lists the signals included in the core10100_ahbapb core. all signals listed in table 3-5 conform to the amba specification rev. 2.0. txd out 4 transmit data the txd[0] signal is the least significant bit. in rmii mode txd[1:0] is used. in rmii mode, txd[1:0] is synchronous to rmii_clk. the txd bus is synchronous to the clkt in mii mode. rmii_clk in rise 50 mhz 50 ppm clock source shared with rmii phy. this input is used only in rmii mode. in mii mode, this input wi ll be grounded by smartdesign. crs_dv in high carrier sense/receive data valid for rmii phy table 3-4 signals incl uded in core10100 and co re10100_ahbapb (continued) name type polarity / bus size description table 3-5 core10100_ahbapb signals name type description apb interface (cpu register access) pclk in apb clock presetn in apb reset (active low and asynchronous) psel in apb select penable in apb enable pwrite in apb write paddr in [7:0] apb address pwdata in [apb_dwidthC1:0] apb write data prdata out [apb_dwidthC1:0] apb read data ahb interface (memory access) hclk in ahb clock hresetn in ahb reset (active low and asynchronous) hwrite out ahb write haddr out [ahb_awidthC1:0] ahb address hready in ahb ready htrans out [1:0] ahb transfer type hsize out [2:0] ahb transfer size hburst out [2:0] ahb burst size hprot out [3:0] ahb protection; set to '0000' hresp in [1:0] ahb response hwdata out [ahb_dwidthC1:0] ahb data out hrdata in [ahb_dwidthC1:0] ahb data in hbusreq out ahb bus request hgrant in ahb bus grant
v4.0 27 4 software interface register maps control and status register addressing the control and status registers are located physically inside core10100 and can be accessed directly by a host via an 8-, 16- or 32-bit interface. all the csrs are 32 bits long and quadword-aligned. the address bus of the csr interface is 8 bits wide, and only bits 6C0 of the location code shown in table 4-1 are used to decode the csr register address. csr definitions table 4-1 csr locations register address reset value description csr0 00h fe000000h bus mode csr1 08h 00000000h transmit poll demand csr2 10h 00000000h receive poll demand csr3 18h ffffffffh receive list base address csr4 20h ffffffffh transmit list base address csr5 28h f0000000h status csr6 30h 32000040h operation mode csr7 38h f3fe0000h interrupt enable csr8 40h e0000000h missed frames and overflow counters csr9 48h fff483ffh mii management csr10 50h 00000000h reserved csr11 58h fffe0000h timer and interrupt mitigation control note: csr9 bits 19 and 2 reset values are dependent on the mdi and sdi inputs. the above assumes mdi is high and sdi is low. table 4-2 bus mode register (csr0) bits 31:24 bits 23:16 dbo tap bits 15:8 pbl bits 7:0 ble dsl bar swr note: the csr0 register has unimplemented bits (shaded). if these bits are read, they will return a predefined value. writing to these bits has no effect.
software interface core10100 v4.0 28 v4.0 table 4-3 bus mode register bit functions bit symbol function csr0.20 dbo descriptor byte ordering mode: 1 C big-endian mode used for data descriptors 0 C little-endian mode us ed for data descriptors csr0.(19..17) tap transmit automatic polling if tap is written with a nonzero value, core10100 performs an automatic transmit descriptor polling when operating in suspende d state. when the descriptor is available, the transmit process goes into running state. when the descriptor is marked as owned by the host, the transmit pr ocess remains suspended. the poll is always performed at the current tr ansmit descriptor list position. the time interval between two consec utive polls is shown in table 4-4 on page 29 . csr0.(13..8) pbl programmable burst length specifies the maximum number of words that can be transferred within one dma transaction. values permissible are 0, 4, 8, 16 and 32. when the value 0 is written, the bursts are limited only by the internal fifos threshold levels. the width of the single word is equal to the csrwidth generic parameter; i.e., all data transfers always use the maximum data bus width. note that pbl is valid only for the data buffers. the data descriptor burst length depends on the datawidth parameter. the rule is that every descriptor field (32-bit) is accessed with a single burst cycle. for da tawidth = 32, the descriptors are accessed with a single 32-bit word transaction; for datawidth = 16, a burst of two 16-bit words; and for datawidth = 8, a burst of four 8-bit words. csr0.7 ble big/little endian selects the byte-ordering mode used by the data buffers. 1 C big-endian mode used for the data buffers 0 C little-endian mode used for the data buffers csr0.(6..2) dsl descriptor skip length specifies the number of longwords between two consecutive descriptors in a ring structure. csr0.1 bar bus arbitration scheme 1 C transmit and receive processes ha ve equal priority to access the bus. 0 C intelligent arbitration, where the receive pr ocess has priority over the transmit process csr0.0 swr software reset setting this bit resets all internal flip-flops. the processor should write a '1' to this bit and then wait until a read returns a '0', indicating that the reset has completed. this bit will remain set for several clock cycles.
core10100 v4.0 register maps v4.0 29 table 4-4 transmit automatic polling intervals csr0.(19..17) 10 mbps 100 mbps 000 tap disabled tap disabled 001 819 s 81.9 s 010 2,450 s 245 s 011 5,730 s 573 s 100 51.2 s 5.12 s 101 102.4 s 10.24 s 110 153.6 s 15.36 s 111 358.4 s 35.84 s table 4-5 transmit poll demand register (csr1) bits 31:24 tpd(31..24) bits 23:16 tpd(23..16) bits 15:8 tpd(15..8) bits 7:0 tpd(7..0) table 4-6 transmit poll demand bit functions bit symbol function csr1.(31..0) tpd writing this field with any value instructs core10100 to check for frames to be transmitted. this operation is valid only when the transmit process is suspended. if no descriptor is available, the transmit process remains suspended. when the descriptor is available, the tran smit process goes into the running state. table 4-7 receive poll demand register (csr2) bits 31:24 rpd(31..24) bits 23:16 rpd(23..16) bits 15:8 rpd(15..8) bits 7:0 rpd(7..0) table 4-8 receive poll demand bit functions bit symbol function csr2.(31..0) rpd writing this field with any value instructs co re10100 to check for receive descriptors to be acquired. this operation is valid only when the receive process is suspended. if no descriptor is available, th e receive process remains suspended. when the descriptor is available, the rece ive process goes into the running state.
software interface core10100 v4.0 30 v4.0 table 4-9 receive descriptor list base address register (csr3) bits 31:24 rla(31..24) bits 23:16 rla(23..16) bits 15:8 rla(15..8) bits 7:0 rla(7..0) table 4-10 receive descriptor list base address register bit functions bit symbol function csr3.(31..0) rla start of the receive list address contains the address of the first descriptor in a receive descriptor list. this address must be longword-aligned (rla(1..0) = 00). table 4-11 transmit descriptor li st base address register (csr4) bits 31:24 tla(31..24) bits 23:16 tla(23..16) bits 15:8 tla(15..8) bits 7:0 tla(7..0) table 4-12 transmit descriptor list base address register bit functions bit symbol function csr4.(31..0) tla start of the transmit list address contains the address of the first descriptor in a transmit descriptor list. this address must be longword-aligned (tla(1..0) = 00). table 4-13 status register (csr5) bits 31:24 bits 23:16 ts rs nis bits 15:8 ais eri gte eti rps bits 7:0 ru ri unf tu tps ti note: the csr5 register has unimplemented bits (shaded). if these bits are read, they wi ll return a predefined value. writing to these bits has no effect.
core10100 v4.0 register maps v4.0 31 table 4-14 status register bit functions bit symbol function csr5.(22..20) ts transmit process state (read-only) indicates the current state of a transmit process: 000 C stopped; reset or stop transmit command issued 001 C running, fetching the transmit descriptor 010 C running, waiting for end of transmission 011 C running, transferring data buffer from host memory to fifo 100 C reserved 101 C running, setup packet 110 C suspended; fifo underflow or unavailable descriptor 111 C running, closing transmit descriptor csr5.(19..17) rs receive process state (read-only) indicates the current state of a receive process: 000 C stopped; reset or stop receive command issued 001 C running, fetching the receive descriptor 010 C running, waiting for the end-of-receive packet before prefetch of the next descriptor 011 C running, waiting for the receive packet 100 C suspended, unavailable receive buffer 101 C running, closing the receive descriptor 110 C reserved 111 C running, transferring data from fifo to host memory csr5.16 nis normal interrupt summary this bit is a logical or of the following bits: csr5.0 C transmit interrupt csr5.2 C transmit buffer unavailable csr5.6 C receive interrupt csr5.11 C general-purpose timer overflow csr5.14 C early receive interrupt only the unmasked bits affect the normal interrupt summary bit. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.15 ais abnormal interrupt summary this bit is a logical or of the following bits: csr5.1 C transmit process stopped csr5.5 C transmit underflow csr5.7 C receive buffer unavailable csr5.8 C receive process stopped csr5.10 C early transmit interrupt only the unmasked bits affect the abnormal interrupt summary bit. the user can clear this bit by writing a 1. writing a 0 has no effect.
software interface core10100 v4.0 32 v4.0 csr5.14 eri early receive interrupt set when core10100 fills the data buffers of the first descriptor. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.11 gte general-purpose timer expiration gets set when the general-purpose timer reaches zero value. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.10 eti early transmit interrupt indicates that the packet to be transmitted was fully transferred into the fifo. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.8 rps receive process stopped rps is set when a receive process enters a stopped state. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.7 ru receive buffer unavailable when set, indicates that the next receive descriptor is owned by the host and is unavailable for core10100. when ru is set, core10100 enters a suspended state and returns to receive descriptor processing when the host change s ownership of the descriptor. either a receive-poll-demand command is issued or a new frame is recognized by core10100. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.6 ri receive interrupt indicates the end of a frame receive. the complete frame has been transferred into the receive buffers. assertion of the ri bit can be delayed using the receive interrupt mitigation counter/timer (csr11.nrp/csr11.rt). the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.5 unf transmit underflow indicates that the transmit fifo was empty during a transmission. the transmit process goes into a suspended state. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.2 tu transmit buffer unavailable when set, tu indicates that the host owns the next descriptor on the transmit descriptor list; therefore, it cannot be used by core10100. when tu is set, the transmit process goes into a suspended state and can resume norm al descriptor processing when the host changes ownership of the descriptor. either a transmit-poll-demand command is issued or transmit automatic polling is enabled. the user can clear this bit by writing a 1. writing a 0 has no effect. table 4-14 status register bit functions (continued) bit symbol function
core10100 v4.0 register maps v4.0 33 csr5.1 tps transmit process stopped tps is set when the transmit pr ocess goes into a stopped state. the user can clear this bit by writing a 1. writing a 0 has no effect. csr5.0 ti transmit interrupt indicates the end of a frame transmission process. assertion of the ti bit can be delayed using the transmit interrupt mitigation counter/timer (csr11.ntp/csr11.tt). the user can clear this bit by writing a 1. writing a 0 has no effect. table 4-15 operation mode register (csr6) bits 31:24 ra bits 23:16 ttm sf bits 15:8 tr st fd bits 7:0 pm pr if pb ho sr hp note: the csr6 register has unimplemented bits (shaded). if these bits are read, they will return a predefined value. writing to these bits has no effect. table 4-16 operation mode register bit functions bit symbol function csr6.30 ra receive all when set, all incoming frames are received , regardless of their destination address. an address check is performed, and the result of the check is written into the receive descriptor (rdes0.30). csr6.22 ttm transmit threshold mode 1 C transmit fifo threshold set for 100 mbps mode 0 C transmit fifo threshold set for 10 mbps mode in rmii mode, this bit is also used to select the frequency of both transmit and receive clocks between 2.5 mhz and 25 mhz. this bit can be changed only when a tr ansmit process is in a stopped state. csr6.21 sf store and forward when set, the transmission starts after a full packet is written into the transmit fifo, regardless of the current fifo threshold level. this bit can be changed only when the transmit process is in the stopped state. csr6.(15..14) tr threshold control bits these bits, together with ttm, sf, and ps, control the threshold level for the transmit fifo. table 4-14 status register bit functions (continued) bit symbol function
software interface core10100 v4.0 34 v4.0 csr6.13 st start/stop transmit command setting this bit when the transmit process is in a stopped state causes a transition into a running state. in the running state, core10100 checks the transmit descriptor at a current descriptor list position. if core10100 owns the descriptor, then the data starts to transfer from memory into the internal transmit fifo. if the host owns the descriptor, core10100 enters a suspended state. clearing this bit when the transmit proc ess is in a running or suspended state instructs core10100 to enter the stopped state. core10100 does not go into the stopped state immediately after clearing the st bit; it will finish the transmission of the frame data corresponding to current descriptor and then moves to stopped state. the status bits of the csr5 register shou ld be read to check the actual transmit operation state. before giving the stop transmit command, the transmit state machine in csr5 can be checked. if the transmission state machine is in suspended state, the stop transmit command can be given so that complete frame transmission by mac is ensured. csr6.9 fd full-duplex mode: 0 C half-duplex mode 1 C forcing full-duplex mode changing of this bit is allowed only when both the transmitter and receiver processes are in the stopped state. csr6.7 pm pass all multicast when set, all frames with multicast destination addresses will be received, regardless of the address check result. csr6.6 pr promiscuous mode when set, all frames will be received regardless of the address check result. an address check is not performed. csr6.4 if inverse filtering (read-only) if this bit is set when working in a perfect filtering mode, the receiver performs an inverse filtering during the address check process. the filtering type bits of the setup frame determine the state of this bit. csr6.3 pb pass bad frames when set, core10100 transfers all frames into the data buffers, regardless of the receive errors. this allows the runt frames, collided fragments, and truncated frames to be received. csr6.2 ho hash-only filtering mode (read-only) when set, core10100 performs an imperfect filtering over both the multicast and physical addresses. the filtering type bits of the setup frame determine the state of this bit. table 4-16 operation mode register bit functions (continued) bit symbol function
core10100 v4.0 register maps v4.0 35 table 4-17 lists all possible combinations of th e address filtering bits. the actual values of the if, ho, and hp bits are determined by the filtering type (ft1Cft0) bits in the setup frame, as shown in table 4-37 on page 50 . the if, ho, and hp bits are read-only. csr6.1 sr start/stop receive command setting this bit enables the reception of the frame by core10100 and the frame is written into the receive fifo. if the bit is not enabled, then the frame is not written into the receive fifo. setting this bit when the receive process is in a stopped state causes a transition into a running state. in the running state, core10100 checks the receive descriptor at the current descriptor list position. if core 10100 owns the descriptor, it can process an incoming frame. when the host owns the de scriptor, the receiver enters a suspended state and also sets the csr5.7 (receive buffer unavailable) bit. clearing this bit when the receive process is in a running or suspended state instructs core10100 to enter a stopped state after receiving the current frame. core10100 does not go into the stopped state immediately after clearing the sr bit. core10100 will finish all pending receive operations before going into the stopped state. the status bits of the csr5 register should be read to check the actual receive operation state. csr6.0 hp hash/perfect receive filtering mode (read-only) 0 C perfect filtering of the incoming frames is performed according to the physical addresses specified in a setup frame. 1 C imperfect filtering over the frames with the multicast addresses is performed according to the hash table specified in a setup frame. a physical address check is performed acco rding to the csr6.2 (ho, hash-only) bit. when both the ho and hp bits are set, an imperfect filtering is performed on all of the addresses. the filtering type bits of the setup frame determine the state of this bit. table 4-17 receive address filtering modes summary pm csr6.7 pr csr6.6 if csr6.4 ho csr6.2 hp csr6.0 current filtering mode 0 0 0 0 0 16 physical addresses C perfect filtering mode 0 0001 one physical address for physical addresses and 512-bit hash table for multicast addresses 0 0 0 1 1 512-bit hash table for both physical and multicast addresses 0 0 1 0 0 inverse filtering x 1 0 0 x promiscuous mode 0 1 0 1 1 promiscuous mode 1 0 0 0 x pass all multicast frames 1 0 0 1 1 pass all multicast frames table 4-16 operation mode register bit functions (continued) bit symbol function
software interface core10100 v4.0 36 v4.0 table 4-18 lists the transmit fifo threshold leve ls. these levels are specified in bytes. table 4-18 transmit fifo threshold levels (bytes) csr6.21 csr6.15..14 csr6.22 = 1 csr6.22 = 0 0 00 64 128 0 01 128 256 0 10 128 512 0 11 256 1024 1 xx store and forward store and forward table 4-19 interrupt enable register (csr7) bits 31:24 bits 23:16 nie bits 15:8 aie ere gte ete rse bits 7:0 rue rie une tue tse tie note: the csr7 register has unimplemented bits (shaded). if these bits are read, they will return a predefined value. writing to these bits has no effect. table 4-20 interrupt enable register bit function bit symbol function csr7.16 nie normal interrupt summary enable when set, normal interrupts are enable d. normal interrupts are listed below: csr5.0 C transmit interrupt csr5.2 C transmit buffer unavailable csr5.6 C receive interrupt csr5.11 C general-purpose timer expired csr5.14 C early receive interrupt csr7.15 aie abnormal interrupt summary enable when set, abnormal interrupts are enable d. abnormal interrupts are listed below: csr5.1 C transmit process stopped csr5.5 C transmit underflow csr5.7 C receive buffer unavailable csr5.8 C receive process stopped csr5.10 C early transmit interrupt csr7.14 ere early receive interrupt enable when both the ere and nie bits are set, early receive interrupt is enabled.
core10100 v4.0 register maps v4.0 37 csr7.11 gte general-purpose timer overflow enable when both the gte and nie bits are set, the general-purpose timer overflow interrupt is enabled. csr7.10 ete early transmit interrupt enable when both the ete and aie bits are set, the early transmit interrupt is enabled. csr7.8 rse receive stopped enable when both the rse and aie bits are set, the receive stopped interrupt is enabled. csr7.7 rue receive buffer unavailable enable when both the rue and aie bits are set, the receive buffer unavailable is enabled. csr7.6 rie receive interrupt enable when both the rie and nie bits are set, the receive interrupt is enabled. csr7.5 une underflow interrupt enable when both the une and aie bits are set, the transmit underflow interrupt is enabled. csr7.2 tue transmit buffer unavailable enable when both the tue and nie bits are set, the tr ansmit buffer unavailable interrupt is enabled. csr7.1 tse transmit stopped enable when both the tse and aie bits are set, the transmit process stopped interrupt is enabled. csr7.0 tie transmit interrupt enable when both the tie and nie bits are set, the transmit interrupt is enabled. table 4-21 missed frames and overflow counter register (csr8) bits 31:24 oco foc(10..7) bits 23:16 foc(6..0) mfo bits 15:8 mfc(15..8) bits 7:0 mfc(7..0) note: the csr8 register has unimplemented bits (shaded). if these bits are read they will return a predefined value. writing to these bits has no effect. table 4-20 interrupt enable re gister bit function (continued) bit symbol function
software interface core10100 v4.0 38 v4.0 table 4-22 missed frames and ov erflow counter bit functions bit symbol function csr8.28 oco overflow counter overflow (read-only) gets set when the fifo overflow counter overflows. resets when the high byte (bits 31:24) is read. csr8.(27..17) foc fifo overflow counter (read-only) counts the number of frames not accepted due to the receive fifo overflow. the counter resets when the high byte (bits 31:24) is read. csr8.16 mfo missed frame overflow set when a missed frame counter overflows. the counter resets when the high byte (bits 31:24) is read. csr8.(15..0) mfc missed frame counter (read-only) counts the number of frames not accepted due to the unavailability of the receive descriptor. the counter resets when the high byte (bits 31:24) is read. the missed frame counter increments when the internal frame cache is full and the descriptors are not available. table 4-23 mii management and serial rom interface register (csr9) bits 31:24 bits 23:16 mdi mden mdo mdc bits 15:8 bits 7:0 sdo sdi sclk scs note: the csr9 register has unimplemented bits (shaded). if these bits are read they will return a predefined value. writing to these bits has no effect. table 4-24 mii management and se rial rom register bit functions bit symbol function csr9.19 mdi mii management data in signal (read-only) this bit reflects the sample on the mdi port during the read operation on the mii management interface. csr9.18 mden mii management operation mode 1 C indicates that core10100 reads the mii phy registers 0 C indicates that core10100 writes to the mii phy registers this register bit directly drives the top-level md en pin. it is intended to be the active low tristate enable for the mdio data output. csr9.17 mdo mii management write data the value of this bit drives the mdo port when a write operation is performed. csr9.16 mdc mii management clock the value of this bit drives the mdc port.
core10100 v4.0 register maps v4.0 39 the mii management interface can be used to control the external phy device from the host side. it allows access to all of the internal phy registers via a simple two-wire interface. there are two signals on the mii management interface: the mdc (management data clock) and the mdio (management data i/o). the ieee 802.3 indirection tristate signal defines the mdio. core10100 uses four unidirectional external signals to control the management interface. for proper operation of the interface, the user must connect a tris tate buffer with an active low enable (inside or outside the fpga), as shown in figure 4-1 . the serial rom interface can be used to access an external serial rom device via csr9. the user can supply an external serial rom device, as shown in figure 4-2 on page 39 . the serial rom can be used to store user data, such as ethernet addresses. note that all access sequences and timing of the serial rom interface are handled by the software. if the serial rom interface is not used, the sdi input port should be connected to logic 0 and the output ports (scs, sclk, and sdo) should be left unconnected. figure 4-1 i/o tristate buffer connections figure 4-2 external serial rom connections csr9.3 sdo serial rom data output the value of this bit drives the sdo port of core10100. csr9.2 sdi serial rom data input this bit reflects the sdi port of core10100. csr9.1 sclk serial rom clock the value of this bit drives the sclk port of core10100. csr9.0 scs serial rom chip select the value of this bit drives the scs port of core10100. table 4-24 mii management and serial rom register bit functions (continued) bit symbol function mdio mden mdo mdc mdi core10100 mdc mii management data input scs sclk sdo core10100 data output serial rom sdi chip select clock
software interface core10100 v4.0 40 v4.0 table 4-25 general-purpose timer and inte rrupt mitigation con trol register (csr11) bits 31:24 cs tt ntp bits 23:16 rt nrp con bits 15:8 tim(15..8) bits 7:0 tim(7..0) table 4-26 general-purpose timer and inte rrupt mitigation co ntrol bit functions bit symbol function csr11.31 cs cycle size controls the time units for the transmit and receive timers according to the following: 1 C mii 100 mbps mode C 5.12 s mii 10 mbps mode C 51.2 s 0 C mii 100 mbps mode C 81.92 s mii 10 mbps mode C 819.2 s csr11.(30..27) tt transmit timer controls the maximum time that must elapse between the end of a transmit operation and the setting of the csr5.ti (transmit interrupt) bit. this time is equal to tt (16 cs). the transmit timer is enabled when written with a nonzero value. after each frame transmission, the timer starts to count down if it has not already started. it is reloaded after every transmitted frame. writing 0 to this field disables the timer effect on the transmit interrupt mitigation mechanism. reading this field gives the actual count value of the timer. csr11.(26..24) ntp number of transmit packets controls the maximum number of frames transmitted before setting the csr5.ti (transmit interrupt) bit. the transmit counter is enabled when written with a nonzero value. it is decremented after every transmitted frame. it is reloaded after setting the csr5.ti bit. writing 0 to this field disables the counter effect on the transmit interrupt mitigation mechanism. reading this field gives the actual count value of the counter.
core10100 v4.0 frame data and descriptors v4.0 41 frame data and descriptors descriptor / data buffer architecture overview a data exchange between the host and core10100 is performed via the descriptor lists and data buffers, which reside in the system shared ram. the buffers hold the host data to be transmitted or received by core10100. the descriptors act as pointers to these buffers. each descri ptor list should be constructed by the ho st in a shared memory area and can be of an arbitrary size. there is a separate list of desc riptors for both the transmit and receive processes. the position of the first descriptor in the descriptor list is described by csr3 for the receive list and by csr4 for the transmit list. the descriptors can be arranged in either a chained or a ring structure. in a chained structure, every descriptor contains a pointer to the next de scriptor in the list. in a ring structure, the address of the next descriptor is determined by csr0.(6..2) (dsldescriptor skip length). every descriptor can point to up to two data buffers. when using descriptor chaining, the address of the second buffer is used as a pointer to the ne xt descriptor; thus, only one buffer is available. a frame can occupy one or more data descriptors and buffers, but one descriptor cannot exceed a csr11.(23..20) rt receive timer controls the maximum time that must elapse between the end of a receive operation and the setting of the csr5.ri (receive interrupt) bit. this time is equal to rt cs. the receive timer is enabled when written with a nonzero value. after each frame reception, the timer starts to count down if it has not already started. it is reloaded after every received frame. writing 0 to this field disables the timer effect on the receive interrupt mitigation mechanism. reading this field gives the actual count value of the timer. csr11.(19..17) nrp number of receive packets controls the maximum number of received frames before setting the csr5.ri (receive interrupt) bit. the receive counter is enabled when written with a nonzero value. it is decremented after every received frame. it is reloaded after setting the csr5.ri bit. writing 0 to this field disables the timer effect on the receive interrupt mitigation mechanism. reading this field gives the actual count value of the counter. csr11.16 con continuous mode 1 C general-purpose timer works in continuous mode 0 C general-purpose timer works in one-shot mode this bit must always be written before the timer value is written. csr11.(15..0) tim timer value contains the number of iterations of the general-purpose timer. each iteration duration is as follows: mii 100 mbps mode C 81.92 s mii 10 mbps mode C 819.2 s table 4-26 general-purpose time r and interrupt mitigation cont rol bit function s (continued) bit symbol function
software interface core10100 v4.0 42 v4.0 single frame. in a ring structure, the descriptor operation ma y be corrupted if only one desc riptor is used. additionally, in the ring structure, at least two descri ptors must be set up by the host. in a transmit process, the host can give the ownership of the first descriptor to core10100 and causes the data specified by the first descriptor to be transmitted. at the same time, the host holds the ownership of the second or last descriptor to itself. this is done to prevent core10100 from fetching the next frame until the host is ready to transmit the data specified in the second descriptor. in a receive process, the ownership of all available descriptors, unless it is pending proc essing by the host, must be given to core10100. core10100 can store a maximum of two frames in the transm it data fifo, including the frame waiting inside the transmit data fifo, the frame being transferred from the da ta interface into the transmit data fifo, and the frame being transmitted out via the mii interface from the transmit data fifo. core10100 can store a maximum of four frames in the receive data fifo, including the frame waiting inside the receive data fifo, the frame being transferred to the data interface from the receive data fifo, and the frame being received via the mii interface into the receive data fifo. figure 4-3 descripto rs in ring structure own csr3/csr4 ? descriptor list base dsl ? descriptor skip csr shared csr buffer 1 buffer 2 rin buffer 1 buffer 2 rin own buffer 1 rin own buffer 2 data data data
core10100 v4.0 frame data and descriptors v4.0 43 figure 4-4 descriptors in chained structure table 4-27 receive descriptors rdes0 own status rdes1 control rbs2 rbs1 rdes2 rba1 rdes3 rba2 csr3/csr4 ? descriptor list base csr buffer 1 buffer 2 rin own buffer 1 buffer 2 rin own buffer 1 buffer 2 rin own data data data shared
software interface core10100 v4.0 44 v4.0 table 4-28 status (rdes0) bit functions bit symbol function rdes0.31 own ownership bit 1 C core10100 owns the descriptor. 0 C the host owns the descriptor. core10100 will clear this bit when it completes a current frame reception or when the data buffers associated with a given descriptor are already full. rdes0.30 ff filtering fail when set, indicates that a received frame did not pass the address recognition process. this bit is valid only for the last descri ptor of the frame (rdes0.8 set), when the csr6.30 (receive all) bit is set and the frame is at least 64 bytes long. rdes0.(29..16) fl frame length indicates the length, in bytes, of the data transferred into a host memory for a given frame this bit is valid only when rdes0.8 (last descriptor) is set and rdes0.14 (descriptor error) is cleared. rdes0.15 es error summary this bit is a logical or of the following bits: rdes0.1 C crc error rdes0.6 C collision seen rdes0.7 C frame too long rdes0.11 C runt frame rdes0.14 C descriptor error this bit is valid only when rdes0.8 (last descriptor) is set. rdes0.14 de descriptor error set by core10100 when no receive buffer was available when trying to store the received data. this bit is valid only when rdes0.8 (last descriptor) is set. rdes0.11 rf runt frame when set, indicates that the frame is damaged by a collision or by a premature termination before the en d of a collision window. this bit is valid only when rdes0.8 (last descriptor) is set. rdes0.10 mf multicast frame when set, indicates that the frame has a multicast address. this bit is valid only when rdes0.8 (last descriptor) is set. rdes0.9 fs first descriptor when set, indicates that this is the first descriptor of a frame. rdes0.8 ls last descriptor when set, indicates that this is the last descriptor of a frame.
core10100 v4.0 frame data and descriptors v4.0 45 rdes0.7 tl frame too long when set, indicates that a current frame is longer than maximum size of 1,518 bytes, as specified by 802.3. tl (frame too long) in the receive descriptor has been set when the received frame is longer than 1,518 bytes. this flag is vali d in all receive descriptors when multiple descriptors are used for one frame. rdes0.6 cs collision seen when set, indicates that a late collision was seen (collision after 64 bytes following sfd). this bit is valid only when rdes0.8 (last descriptor) is set. rdes0.5 ft frame type when set, indicates that the frame has a length field larger than 1,500 (ethernet-type frame). when cleared, indicates an 802.3-type frame. this bit is valid only when rdes0.8 (last descriptor) is set. additionally, ft is invalid for runt frames shorter than 14 bytes. rdes0.3 re report on mii error when set, indicates that an error has been detected by a physical layer chip connected through the mii interface. this bit is valid only when rdes0.8 (last descriptor) is set. rdes0.2 db dribbling bit when set, indicates that the frame was not byte-aligned. this bit is valid only when rdes0.8 (last descriptor) is set. rdes0.1 ce crc error when set, indicates that a crc error has occurred in the received frame. this bit is valid only when rdes0.8 (last descriptor) is set. additionally, ce is not valid when the received frame is a runt frame. rdes0.0 zero this bit is reset for frames with a legal length. table 4-28 status (rdes0) bit functions (continued) bit symbol function
software interface core10100 v4.0 46 v4.0 table 4-29 control and count (rdes1) bit bit symbol function rdes1.25 rer receive end of ring when set, indicates that this is the last de scriptor in the receive descriptor ring. core10100 returns to the first descriptor in the ring, as specified by csr3 (start of receive list address). rdes1.24 rch second address chained when set, indicates that the second buffer's address points to the next descriptor and not to the data buffer. note that rer takes precedence over rch. rdes1.(21..11) rbs2 buffer 2 size indicates the size, in bytes, of memory space used by the second data buffer. this number must be a multiple of four. if it is 0, core10100 ignores the second data buffer and fetches the next data descriptor. this number is valid only when rdes1.24 (second address chained) is cleared. rdes1.(10..0) rbs1 buffer 1 size indicates the size, in bytes, of memory space used by the first data buffer. this number must be a multiple of four. if it is 0, co re10100 ignores the first data buffer and uses the second data buffer. table 4-30 rba1 (rdes2) bit functions bit symbol function rdes2.(31..0) rba1 receive buffer 1 address indicates the length, in bytes, of memory allocated for the first receive buffer. this number must be longword-aligned (rdes2.(1..0) = '00'). table 4-31 rba2 (rdes3) bit functions bit symbol function rdes3.(31..0) rba2 receive buffer 2 address indicates the length, in bytes, of memory allocated for the second receive buffer. this number must be longword-aligned (rdes3.(1..0) = '00'). table 4-32 transmit descriptors tdes0 own status tdes1 control tbs2 tbs1 tdes2 tba1 tdes3 tba2
core10100 v4.0 frame data and descriptors v4.0 47 table 4-33 status (tdes0) bit functions bit symbol function tdes0.31 own ownership bit 1 C core10100 owns the descriptor. 0 C the host owns the descriptor. core10100 will clear this bit when it completes a current frame transmission or when the data buffers associated with a given descriptor are empty. tdes0.15 es error summary this bit is a logical or of the following bits: tdes0.1 C underflow error tdes0.8 C excessive collision error tdes0.9 C late collision tdes0.10 C no carrier tdes0.11 C loss of carrier this bit is valid only when tdes1.30 (last descriptor) is set. tdes0.11 lo loss of carrier when set, indicates a loss of th e carrier during a transmission. this bit is valid only when tdes1.30 (last descriptor) is set. tdes0.10 nc no carrier when set, indicates that the carrier was not as serted by an external transceiver during the transmission. this bit is valid only when tdes1.30 (last descriptor) is set. tdes0.9 lc late collision when set, indicates that a collision was detected after transmitting 64 bytes. this bit is not valid when tdes0.1 (underflow error) is set. this bit is valid only when tdes1.30 (last descriptor) is set. tdes0.8 ec excessive collisions when set, indicates that the transmission was aborted after 16 retries. this bit is valid only when tdes1.30 (last descriptor) is set. tdes0.(6..3) cc collision count this field indicates the number of collisions that occurred before the end of a frame transmission. this value is not valid when tdes0.8 (excessive collisio ns bit) is set. this bit is valid only when tdes1.30 (last descriptor) is set.
software interface core10100 v4.0 48 v4.0 tdes0.1 uf underflow error when set, indicates that the fifo was empty during the frame transmission. this bit is valid only when tdes1.30 (last descriptor) is set. tdes0.0 de deferred when set, indicates that the frame was deferr ed before transmission. deferring occurs if the carrier is detected when the transmission is ready to start. this bit is valid only when tdes1.30 (last descriptor) is set. table 4-34 control (t des1) bit functions bit symbol function tdes1.31 ic interrupt on completion setting this flag instructs core10100 to set csr5.0 (transmit interrupt) immediately after processing a current frame. this bit is valid when tdes1.30 (last descriptor) is set or for a setup packet. tdes1.30 ls last descriptor when set, indicates the last descriptor of the frame. tdes1.29 fs first descriptor when set, indicates the first descriptor of the frame. tdes1.28 ft1 filtering type this bit, together with tdes0.22 (ft0), controls a current filtering mode. this bit is valid only for the setup frames. tdes1.27 set setup packet when set, indicates that this is a setup frame descriptor. tdes1.26 ac add crc disable when set, core10100 does not append the crc value at the end of the frame. the exception is when the frame is shorter than 64 bytes and automatic byte padding is enabled. in that case, the crc field is added, despite the state of the ac flag. tdes1.25 ter transmit end of ring when set, indicates the last descriptor in the descriptor ring. tdes1.24 tch second address chained when set, indicates that the second descriptor's address points to the next descriptor and not to the data buffer. this bit is valid only when tdes1.25 (transmit end of ring) is reset. tdes1.23 dpd disabled padding when set, automatic byte padding is disabled. core10100 normally appends the pad field after the info field when the size of an actual frame is less than 64 bytes. after padding bytes, the crc field is also insert ed, despite the state of the ac flag. when dpd is set, no padding bytes are appended. table 4-33 status (tdes0) bit functions (continued) bit symbol function
core10100 v4.0 frame data and descriptors v4.0 49 mac address and setup frames the setup frames define addresses that are used for the receive address filtering process. these frames are never transmitted on the ethernet connection. they are used to fill the address filtering ram. a valid setup frame must be exactly 192 bytes long and mu st be allocated in a single buffer that is longword-aligned. tdesi.27 (setup frame indicator) must be set. both tdes1.29 (first descriptor) and tdes1.30 (last desc riptor) must be cleared for the setup frame. the ft1 and ft0 bits of the setup frame define the current filtering mode. table 4-37 on page 50 lists all possible combinations. table 4-38 on page 50 shows the setup frame buffer format for perfect filtering modes. table 4-39 on page 51 shows the setup frame buffer for imperfect filtering modes. the setup should be sent to core10100 when core10100 is in stop mode. when a ram with more than 192 bytes is used for the address filtering ram, a setup frame with more than 192 bytes can be written into this memory to initialize its contents, tdes1.22 ft0 filtering type this bit, together with tdes0.28 (ft1), controls the current filtering mode. this bit is valid only when the tdes1.27 (set) bit is set. tdes1.(21..11) tbs2 buffer 2 size indicates the size, in bytes, of memory space used by the second data buffer. if it is zero, core10100 ignores the second data buffer and fetches the next data descriptor. this bit is valid only when tdes1.24 (second address chained) is cleared. tdes1.(10..0) tbs1 buffer 1 size indicates the size, in bytes, of memory space used by the first data buffer. if it is 0, core10100 ignores the first data buffer and uses the second data buffer. table 4-35 tba1 (t des2) bit functions bit symbol function tdes2.(31..0) tba1 transmit buffer 1 address contains the address of the first data buffer. for the setup frame, this address must be longword-aligned (tdes3.(1..0) = '00'). in al l other cases, there are no restrictions on buffer alignment. table 4-36 tba2 (t des3) bit functions bit symbol function tdes3(31..0) tba2 transmit buffer 2 address contains the address of the second data buffer. there are no restrictions on buffer alignment. table 4-34 control (tdes1) bit functions (continued) bit symbol function
software interface core10100 v4.0 50 v4.0 but only the first 192 bytes constitute the address filtering operation. while writing the setup frame buffer in the host memory, the buffer size must be twice the size of the setup frame buffer. table 4-37 filtering type selection ft1 ft0 description 00 perfect filtering mode setup frame buffer is interpreted as a set of sixteen 48-bit physical addresses. 01 hash filtering mode setup frame buffer contains a 512-bit hash table plus a single 48-bit physical address. 10 inverse filtering mode setup frame buffer is interpreted as a set of sixteen 48-bit physical addresses. 11 hash only filtering mode setup frame buffer is interpreted as a 512-bit hash table. table 4-38 perfect filtering setup frame buffer byte number data bits 31:16 data bits 15:0 1:0 {physical address [39:32],physical address [47:40]} 3:2 {physical address [23:16],physical address [31:24]} 5:4 {physical address [7:0],physical address [15:8]} 15:12 xxxxxxxxxxxxxxxx physical address 1 (15:00) 19:16 xxxxxxxxxxxxxxxx physical address 1 (31:16) 23:20 xxxxxxxxxxxxxxxx physical address 1 (47:32) . . . . . . . . . 171:168 xxxxxxxxxxxxxxxx physical address 14 (15:00) 175:172 xxxxxxxxxxxxxxxx physical address 14 (31:16) 179:176 xxxxxxxxxxxxxxxx physical address 14 (47:32) 183:180 xxxxxxxxxxxxxxxx physical address 15 (15:00) 187:184 xxxxxxxxxxxxxxxx physical address 15 (31:16) 191:188 xxxxxxxxxxxxxxxx physical address 15 (47:32)
core10100 v4.0 internal operation v4.0 51 internal operation the address bus width of the receive/transmit data rams can be customized via the core parameters rfifodepth and tfifodepth ( table 3-1 on page 19 ). those memory blocks must be at least as big as the longest frame used on a given network. core10100 stops to request new frame data when there are two frames already in the transmit data ram. it resumes the request for new frame data when there is either one or no frame in the transmit data ram. at any given time, the receive data ram can hold no more than four frames, including frames currently under transfer. dma controller the dma is used to control a data flow between the host and core10100. the dma services the following types of requests from the core10100 transmit and receive processes: ? transmit request: descriptor fetch descriptor closing setup packet processing data transfer from host buffer to transmit fifo ? receive request: table 4-39 hash table setup frame buffer format byte number data bits 31:16 data bits 15:0 3:0 xxxxxxxxxxxxx xxx hash filter (015:000) 7:4 xxxxxxxxxxxxx xxx hash filter (031:016) 11:8 xxxxxxxxxxxxx xxx hash filter (047:032) . . . . . . . . . 123:121 xxxxxxxxxx xxxxxx hash filter (495:480) 127:124 xxxxxxxxxx xxxxxx hash filter (511:496) 131:128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 135:132 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx . . . . . . 159:156 xxxxxxxxxxxxxxxx physical address (15:00) 163:160 xxxxxxxxxxxxxxxx physical address (31:16) 167:164 xxxxxxxxxxxxxxxx physical address (47:32) 171:168 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 175:172 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx . . . . . . 183:180 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 187:184 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 191:188 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx
software interface core10100 v4.0 52 v4.0 descriptor fetch descriptor closing data transfer from receive fifo to host buffer the key task for the dma is to perform an arbitration bet ween the receive and transmit processes. two arbitration schemes are possible according to the csr0.1 bit: ? 1 C round-robin arbitration scheme in which receive and transmit processes have equal priorities ? 0 C the receive process has priority over the transmit proc ess unless transmission is in progress. in this case, the following rules apply: the transmit process request should be serviced by the dma between two consecutive receive transfers. the receive process request should be serviced by the dma between two consecutive transmit transfers. transfers between the host and core10100 performed by the dma component are either single data transfers or burst transfers. for the data descriptors, the data transfer size depends on the core parameter datawidth. the rule is that every descriptor field (32-bit) is accessed with a single burst. for datawidth = 32, the descriptors are accessed with a single transaction; for datawidth = 16, the descriptors are accessed with a burst of two 16-bit words, and for datawidth = 8, the descriptors are accessed with a burst of four 8-bit words. in the case of data buffers, the burst length is defined by csr0.(13..8) (programmable burst length) and can be set to 0, 1, 2, 4, 8, 16, or 32. when set to 0, no maximum burst size is defined, and the transfer ends when the transmit fifos are full or the receive fifos are empty. transmit process the transmit process can operate in one of three modes: running, stopped, or suspended. after a software or hardware reset, or after a stop transmit command, the transmit proce ss is in a stopped state. the transmit process can leave a stopped state only after the start transmit command. when in a running state, the transmit process performs desc riptor/buffer processing. when operating in a suspended or stopped state, the transmit process retains the position of the next descriptor, i.e., the address of the descriptor following the last descriptor being closed. after entering a running state, that position is used for th e next descriptor fetch. the only exception is when the host writes the transmit descriptor base address register (csr4). in that case, the descriptor address is reset and the fetch is directed to the first position in the list. before writing to csr4 the mac must be in a stopped state. when operating in a stopped state, the transmit process stopped (tps) output is high. this output can be used to disable the clkt clock signal external to core10100. when both the tps and receive process stopped (rps) outputs are high, all clock signals except clkcsr can be disabled external to core10100. the transmit process remains running until one of the following events occurs: ? the hardware or software reset is issued. setting the csr0.0 (swr) bit can perform the software reset. after the reset, all the internal registers return to their default states. the cu rrent descriptor's position in the transmit descriptor list is lost. ? a stop transmit command is issued by the host. this can be performed by writing 0 to the csr6.13 (st) bit. the current descriptor's position is retained. ? the descriptor owned by the host is found. the current descriptor's position is retained. ? the transmit fifo underflow error is detected. an underflow error is generated when the transmit fifo is empty during the transmission of the frame. when it occurs, the transmit proce ss enters a suspended state. transmit automatic polling is internally disabled, even if it is enabled by the host by writing the tap bits. the current descriptor's position is retained. leaving a suspended state is possible in one of the following situations: ? a transmit poll demand command is issued. this can be performed by writing csr1 with a nonzero value. the transmit poll demand command can also be generated auto matically when transmit auto matic polling is enabled.
core10100 v4.0 internal operation v4.0 53 transmit automatic polling is enabled on ly if the csr0(19..17) (tap) bits are written with a nonzero value and when there was no underflow error prior to entering the suspended state. ? a stop transmit command is issued by the host. this can be performed by writing 0 to the csr6.13 (st) bit. the current descriptor's position is retained. a typical data flow for the tran smit process is illustrated in figure 4-6 on page 53 . the events for the transmit process typically happen in the following order: 1. the host sets up csr registers for the operational mode, interrupts, etc. 2. the host sets up transmit descriptors/data in the shared ram. 3. the host sends the transmit start command. 4. core10100 starts to fetch the transmit descriptors. 5. core10100 transfers the transmit data to transmit data ram from the shared ram. 6. core10100 starts to transmit data on mii. figure 4-5 transmit process transitions figure 4-6 transmit data flow note: refer to the core10100 users guide for an example of transmit data timing. transmit stopped transmit suspended transmit running start transmit command stop transmit command descriptor unavailable pull demand command underflow error reset command stop transmit command reset command host-sharedram csr_interface data_interface-sharedram data_interface-txfifo_ram transmit_controller-mii txfifo_ram-transmit_controller csrs des+data csr6 tx des tx data tx data preamble tx data tx data crc
software interface core10100 v4.0 54 v4.0 receive process the receive process can operate in one of three modes: running, stopped, or suspended. after a software or hardware reset, or after a stop receive command, the receive process is in the stopped state. the receive process can leave a stopped state only after a start receive command. in the running state, the receiver performs descriptor/buffer processing. in the running state, the receiver fetches from the receive descriptor list. it performs this fetch regardless of whether there is any frame on the link. when there is no frame pending, the receive process reads the descriptor and simply waits for the frames. when a valid frame is recognized, the receive process starts to fill the memory buffers pointed to by the current descriptor. when the frame ends, or when the memory buffers are completely filled, the current frame descriptor is closed (ownership bit cleared). immediately, the next descriptor on the list is fetched in the same manner, and so on. when operating in a suspended or stopped state, the receive process retains the position of the next desc riptor (the address of the descriptor following the last descriptor that was closed). after entering a running state, the retained position is used for the next descriptor fetch. the only ex ception is when the host writes the receive descriptor base address register (csr3). in that case, the descriptor address is reset and the fetch is pointed to the first position in the list. before writing to csr3, the mac must be in a stopped state. when operating in a stopped state, the rps output is high. this output allows for switching the receive clock clkr off externally. when both the rps and tps outputs are high, al l clocks except clkcsr can be externally switched off. the receive process runs until one of the following events occurs: ? a hardware or software reset is issued by the host. a so ftware reset can be performed by setting the csr0.0 (swr) bit. after reset, all internal registers return to their default states. the current descriptor's position in the receive descriptor list is lost. ? a stop receive command is issued by the host. this can be performed by writing 0 to the csr6.1 (sr) bit. the current descriptor's position is retained. ? the descriptor owned by the host is found by core10100 during the descriptor fetch. the current descriptor's position is retained. leaving a suspended state is possible in one of the following situations: ? a receive poll command is issued by the host. this can be performed by writing csr2 with a nonzero value. ? a new frame is detected by core10100 on a receive link. ? a stop receive command is issued by the host. this can be performed by writing 0 to the csr6.1 (sr) bit. the current descriptor's position is retained. the receive state machine goes into stopped state after th e current frame is done if a stop receive command is given. it does not go in to a stopped state immediately.
core10100 v4.0 internal operation v4.0 55 figure 4-7 receive process transitions note: refer to the core10100 users guide for an example of receive timing. a typical data flow in a receive process is illustrated in figure 4-8 on page 55 . the events for the receive process typically happen in the following order: 1. the host sets up csr registers for the operational mode, interrupts, etc. 2. the host sets up receive de scriptors in the shared ram. 3. the host sends the receive start command. 4. core10100 starts to fetch the transmit descriptors. 5. core10100 waits for receive data on mii. 6. core10100 transfers received data to the receive data ram. 7. core10100 transfers received data to shared ram from receive data ram. figure 4-8 receive data flow interrupt controller the interrupt controller uses three internal control and st atus registers: csr5, csr7, and csr11. csr5 contains the core10100 status information. it has 10 bits that can trigger an interrupt. these bits are collected in two groups: normal interrupts and abnormal interrupts. each group has its ow n summary bit, nis and ais, respectively. the nis and ais bits directly control the int output port of core10100. every status bit in csr5 that can source an interrupt can be individually masked by writing an appropriate value to csr7 (interrupt enable register). additionally, an interrupt mitigation mechanism is provided for reducing cpu usage in servicing interrupts. interrupt mitigation is controlled via csr11. there are separate inte rrupt mitigation control blocks for the transmit and receive interrupts. both of these blocks consist of a 4-bit frame counter and a 4-bit timer. the op eration of these blocks is similar for the receive and transmit processes. after the en d of a successful receive or transmission operation, an start receive command stop receive command reset command receive stopped receive running descriptor unavailable stop receive command frame recognized pull demand command reset command receive suspended host-sharedram csr_interface data_interface-sharedram data_interface-rxfifo_ram rxfifo_ram-receive_controller receive_controller-mii csrs csr6 rx des rx data preamble rx data crc rx data rx des rx data crc
software interface core10100 v4.0 56 v4.0 appropriate counter is decremented and the timer starts to co unt down if it has not already started. an interrupt is triggered when either the counter or the timer reaches a zero value. this allows core10100 to generate a single interrupt for a few received/transmitted frames or after a specified ti me since the last successful receive/transmit operation. it is possible to omit transmit interrupt mitigation for one particular frame by setting the interrupt on completion (ic) bit in the last descriptor of the frame. if the ic bit is set, core10100 sets the transmit interrupt immediately after the frame has been transmitted. the int port remains low for a single clock cycle on every write to csr5. this enables the use of both level- and edge- triggered external interrupt controllers. figure 4-9 interrupt scheme int csr11 mitigation control csr5 status csr7 interrupt enable tt = 0 ntp = 0 nrp = 0 rt = 0 ti ri tu tu eti eri gte nis ais tps rps unf tie rie tue rue ete ere gte nie aie tse rse une
core10100 v4.0 internal operation v4.0 57 general-purpose timer core10100 includes a 16-bit general-purpose timer to simplify time interval calculation by an external host. the timer operates synchronously with the transmit clock clkt generated by the phy device. this gives the host the possibility of measuring time intervals based on actual ethernet bit time. the timer can operate in one-shot mode or continuous mode. in one-shot mode, the timer stops after reaching a zero value; in continuous mode, it is automatically reloaded and continues counting down after reaching a zero value. the actual count value can be tested with an accuracy of 1 bit by reading csr11.(15..0). when writing csr11.(15..0), the data is stored in the internal reload register. the timer is immediately reloaded and starts to count down. data link layer operation mii interface core10100 uses a standard mii interface as defined in the 802.3 standard. this interface can be used for connecting core10100 to an external ethernet 10/100 phy device. mii interface signals table 4-40 external phy interface signals ieee 802.3 signal name core10100 signal name description rx_clk clkr clock for receive operation this must be a 25 mhz clock for 100 mbps operation or a 2.5 mhz clock for 10 mbps operation. rx_dv rx_dv receive data valid signal the phy device must assert rx_dv when a valid data nibble is provided on the rxd signal. the rx_dv signal must be synchronous to the clkr receive clock. rx_er rx_er receive error if rx_er is asserted during core10100 rece ption, the frame is received and status of the frame is updated with rx_er. the rx_er signal must be synchronous to the clkr receive clock. rxd rxd receive data recovered and decoded by phy the rxd[0] signal is the least significant bit. the rxd bus must be synchronous to the clkr receive clock. tx_clk clkt clock for transmit operation this must be a 25 mhz clock for 100 mbps operation or a 2.5 mhz clock for 10 mbps operation. tx_en tx_en transmit enable when asserted, indicates vali d data for the phy on txd. the tx_en signal is synchronous to the clkt transmit clock. txd txd transmit data the txd[0] signal is the least significant bit. the txd bus is synchronous to the clkt transmit clock.
software interface core10100 v4.0 58 v4.0 mii receive operation figure 4-10 mii receive operation col col collision detected this signal must be asserted by the ph y when a collision is detected on the medium. it is valid only when operating in a half-duplex mode. when operating in a full-duplex mode, this signal is ignored by core10100. the col signal is not required to be synchronous to either clkr or clkt. the col signal is sampled internally by the clkt clock. crs crs carrier sense this signal must be asserted by the phy when either a receive or a transmit medium is non-idle. the crs signal is not required to be synchronous to either clkr or clkt. tx_er tx_er transmit error the current version of core10100 has the tx_e r signal statically tied to logic 0 (no transmit errors). mdc mdc mii management clock this signal is driven by the csr9.16 bit. mdio mdi mii management data input the state of this signal can be checked by reading the csr9.19 bit. mdo mii management data output this signal is driven by the csr9.18 bit. table 4-40 external phy interface signals (continued) ieee 802.3 signal name core10100 signal name description clkr rx_dv rx_er read points error detected rxd[3:0] data data data data
core10100 v4.0 internal operation v4.0 59 mii transmit operation figure 4-11 mii transmit operation frame format core10100 supports the ethernet frame format shown in figure 4-12 (b indicates bytes). the standard ethernet frames (dix ethernet), as well as ieee 802.3 frames, are accepted. figure 4-12 frame format clkt tx_en col txd[3:0] write points collision detecte d data data data data crs deferring table 4-41 frame field usage field width (bytes) transmit operation r eceive operation preamble 7 generated by core10100 stripped from received data not required for proper operation sfd 1 generated by core10100 stripped from received data da 6 supplied by host checked by core10100 according to current address filtering mode and passed to host sa 6 supplied by host passed to host length/ type 6 supplied by host passed to host data 0-1500 supplied by host passed to host pad 0-46 generated by core10100 when csr.23 (dpd) bit is cleared and data supplied by host is less than 64 bytes passed to host fcs 4 generated by core10100 when csr.26 bit is cleared checked by core10100 and passed to host preamble sfd da sa length / type data pad fcs 7b 1b 6b 6b 2b 46b ? 1500b 4b
software interface core10100 v4.0 60 v4.0 collision handling collision detection is performed via the col input port. if a collision is dete cted before the end of the preamble/ sfd, core10100 completes the preamble/sfd, transmits the jam sequence, and initiates a backoff computation. if a collision is detected after the transmission of the preamble and sfd, but prior to 512 bits being transmitted, core10100 immediately aborts the transmission, transmits the jam sequence, and then initiates a backoff. if a collision is detected after 512 bits have been transmitted, the collision is termed a late collision. core10100 aborts the transmission and appends the jam sequence. the transmit message is flushed from the fifo. core10100 does not initiate a backoff and does not attempt to retransm it the frame when a late collision is detected. core10100 uses a truncated binary exponential backoff algo rithm for backoff computing, as defined in the ieee 802.3 standard and outlined in figure 4-13 . backoff processing is performed only in half-duplex mode. in full-duplex mo de, collision detection is disabled. figure 4-13 backoff process algorithms wait for end of transmission normal collision? increment attempt attempt < 16 attempt < 10 ran = random(0..2 attempt ? 1) ran = random(0..2 10 ? 1) wait for ran * slot time transmission ready set tdes0.8 (ec) excessive collision reset attempt yes no yes no yes no yes no late collision? set tdes0.9 (lc) late collision yes no next transmission attempt
core10100 v4.0 internal operation v4.0 61 deferring the deferment algorithm is implemented per the 802.3 specification and outlined in figure 4-14 . the interframe gap (ifg) timer starts to count whenever the link is not idle. if ac tivity on the link is detected during the first 60 bit times of the ifg timer, the timer is reset and restarted once activity has stopped. during the final 36 bit times of the ifg timer, the link activity is ignored. carrier sensing is performed only when operating in half-duplex mode. in full-duplex mode, the state of the crs input is ignored. figure 4-14 deferment process algorithms reset ifg timer transmit ready and not in backoff? transmit frame yes no yes no yes no yes no ifg timer = 60 bit times? crs = 0? crs = 0? ifg timer = 96 bit times? yes no
software interface core10100 v4.0 62 v4.0 receive address filtering there are three kinds of addresses on the lan: the unicast addresses, the multicast addresses, and the broadcast addresses. if the first bit of the address (ig bit) is 0, the frame is unicast, i.e., dedicated to a single station. if the fir st bit is 1, the frame is multicast, i.e., destined for a group of stations. if the address field contains all ones, the frame is broadcast and is received by all stations on the lan. when core10100 operates in perfect filtering mode, all frames are checked against the addresses in the address filtering ram. the unicast, multicast, and broadcast frames are treated in the same manner. when core10100 operates in the imperfect filtering mode, th e frames with the unicast addresses are checked against a single physical address. the multicast frames are checked using the 512-bit hash table. to receive the broadcast frame, the hash table bit corresponding to the broadcast addres s crc value must be set. core10100 applies the standard ethernet crc function to the first six bytes of the frame tha t contains a destination address. the least significant nine bits of the crc value are used to index the table. if the indexe d bit is set, the frame is accepted. if this bit is cleared, th e frame is rejected. the algorithm is shown in figure 4-15 . figure 4-15 filtering with one physical address and the hash table it is important that one bit in the hash table corresponds to many ethernet addresses. therefore, it is possible that some frames may be accepted by core10100, even if they are not in tended to be received. this is because some frames that should not have been received have addresses that hash to the same bit in the table as one of the proper addresses. the software should perform additional address filtering to reject all such frames. the receive address filtering ram must be enabled using the addrfilter core parameter to enable the above functionality. da ig 802.3 frame destination address 512-bit hash table one physical address multicast address? yes no 47 0 47 crc generator 9 hash table index 0 8
core10100 v4.0 internal operation v4.0 63 steps for calculating crc with hash filtering following are the steps the core is using, and testbench/so ftware needs to follow. these are the steps for calculating crc with which the hash filter logic of the dut accepts the frames properly: 1. initial value of the crc is 0xffffffff. 2. xor the incoming data bit with the 31st bit of the current crc value. 3. left shift the current crc value by one bit. 4. check the xored value from step 2. if this value is 1'b1 then xor the current crc value with the generator polynomial (0x4c11db7). 5. insert the bit value result from step 2 at the 0th bit location of the current crc value. 6. repeat steps 2, 3, 4, and 5 until the crc is calculat ed for all the bits of the data.mii_to_rmii internal architecture external address filtering interface an external address filtering interface is provided to extend the internal filtering capabilities of core10100. the interface allows connection of external user-supplied address checking logic. all signals from the interface are synchronous to the clkr clock. if the external address filtering is not us ed, all input ports of the interface must be grounded and all output ports must be left floating. table 4-42 external address interface description core10100 signal name type description match in external address match when high, indicates that the destination address on the matchdata port is recognized by the external address checking logic and that the current frame should be received by core10100. when low, indicates that the destination address on the matchdata port is not recognized and that the current frame should be discarded. note that the match signal should be valid only when the matchval signal is high. matchval in external address match valid when high, indicates that the match signal is valid. matchen out external match enable when high, indicates that the matchdata signal is valid. the matchen output should be used as an enable signal for the external address checking logic. it is high for at least four clkr clock periods to allow for latency of external address checking logic. matchdata out external address match data the matchdata signal represents the 48-bit destination address of the received frame. note that the matchdata signal is valid only when matchen signal is high.
software interface core10100 v4.0 64 v4.0 mii to rmii interface the 25 mhz transmit clock (clkt) and receive clock (clkr) are derived from the 50 mhz rmii_clk (divide by 2 for 100 mbps operation). the 2.5 mhz transmit clock (clkt) and receive clock (clkr) are derived from the 50 mhz rmii_clk (divide by 20 for 10 mbps operation). the internal clock net clk_tx_rx must be assigned to a global clock network. the csr6 bit 22, which is connected to the speed port in the mii_rmii block, will select the clock frequency as either 2.5 mhz or 25 mhz. the data width on the mii interface is 4 bits for both transm it and receive. the data width on the rmii interface is 2 bits for both transmit and receive. the crs and rx_dv signals are decoded from crs_dv. the col signal is derived from and-ing together the tx_en and the decoded crs signal from the crs_dv line in half duplex mode. figure 4-16 mii_to_rmii internal architecture tx_pipeline divide by 20 divide by 2 rx_pipeline speed 0 1 clkt clkr ref_clk (50 mhz) ref_clk ref_clk txd[1:0] rxd[1:0] mii_txd[3:0] mii_rxd[3:0] 25 mhz 2.5 mhz synchronizer and decoder crs_dv crs rx_dv clkr rx_er mii_rx_er clkt mii_tx_en tx_en mii_tx_en crs col synchronizer clk_tx_rx
v4.0 65 5 interface timing core10100?csr interface csr read/write operation the csr read and write operations are synchronous to the po sitive edge of the clkcsr signal and are illustrated in figure 5-1 . read operations require that the data be read in the same clock cycle in which the csrreq signal is set to logic 1. figure 5-1 csr read/write operation core10100?data interface the data interface is used for data transfers between core 10100 and external shared system memory. it is a master via the dma interface; i.e., core10100 operates as an initiator on this data interface. the interface operates synchronously with the clkdma clock supplied by the system. the data width of the interface can be changed using the core parameter datawidth. possible datawidth values are 8, 16, and 32. there are two data exchange types that can be initiated and performed by core10100 via the dma interface. the first data exchange type is the transmit and receive descriptors. these are set up by the host and fetched by the dma interface to instruct core10100 to exchange the ethernet frame data in specified locations of shared ram. the second data exchange type is the ethernet data type. data interface write operation the data interface supports single or burst data transfer. th e writes are operated on the positive edge of the clock clkdma. the write operation starts when the data interface sets datareq to high, and then the data interface waits until dataack from the host interface is set to high (which indicates that the host is ready to receive the writes). a byte enable signal databe indicates the valid bytes on each write. the signal dataob indicates to the hosts that it is the end of a burst transfer. the signal dataac k can be asserted or deasserted at any clock cycle; even in the middle of a burst transfer. clk csrreq csrrw csrbe csraddr csrdatai csrdatao read data addr be data addr be be addr data write read
interface timing core10100 v4.0 66 v4.0 figure 5-2 core10100 host data write operation data interface read operation the data interface supports single or burst data transfer. the reads are operated on the positive edge of the clock clkdma. the read operation starts when the data interface sets datareq to high, and then the data interface waits until dataack from the host interface is set to high (which indicates that the data is ready to be received by the data interface). a byte enable signal, databe, indicates the valid bytes on each read request. the signal dataob indicates to the hosts that it is the end of a burst transfer. dataack can be asserted or deasserted at any clock cycle, even i n the middle of a burst transfer. figure 5-3 host data read operation clk datareq datarw dataeob databe dataaddr datai datao write end of dataack a+ a+ aa bb write data[a+1] data[a+2] data[a] data[a] clk datareq datarw dataeob databe dataaddr datai datao read end of dataack a+ a+ aa bb data[a] data[a+1] data[a+2] data[a] read
core10100 v4.0 core10100_ahbapb?apb interface v4.0 67 core10100_ahbapb?apb interface figure 5-4 and figure 5-5 depict typical write cycle and read cycle timing relationships relative to the apb system clock, pclk. figure 5-4 data write cycle figure 5-5 data read cycle more detailed descriptions an d timing waveforms can be found in the amba specification: http://www.amba.com/products /solutions/amba_spec.html. pclk psel pwrite penable paddr[4:0] pwdata[7:0] register address register data pclk psel pwrite penable paddr[4:0] pwdata[7:0] register address register data
interface timing core10100 v4.0 68 v4.0 core10100_ahbapb?ahb interface core10100 implements an amba ahbCcompliant master function on the core data interface, allowing the core to access memory for data storage. the ahb inte rface is compliant with the amba specification. figure 5-6 simple transfer more detailed descriptions an d timing waveforms can be found in the amba specification: http://www.amba.com/products /solutions/amba_spec.html. core10100-rmii interface core10100 implements the mii-to-rmii interface, which is compliant with the rmii specification. full timing diagrams are available in the rmii specification: http://www.national.com/appinfo/networks/files/rmii_1_2.pdf clock and reset control clock controls as shown in figure 5-7 on page 69 , there are four clock domains in the design: ? the tc and bd components operate synchronously with the clkt clock supplied by the mii phy device. this is a 2.5 mhz clock for 10 mbps operation or a 25 mhz clock for 100 mbps operation. ? the rc operates synchronously with the clkr clock supplied by the mii phy device. this is a 2.5 mhz clock for 10 mbps operation or a 25 mhz clock for 100 mbps operation. ? the tfifo, rfifo, tlsm, rlsm, and dma components operate synchronously with the clkdma global clock supplied by the system. data (a) data (a) hrdata[31:0] hready hwdata[31:0] c ontrol haddr[31:0] h c lk a dd ress phase data phase c ontrol a
core10100 v4.0 clock and reset control v4.0 69 ? the csr operates synchronously with the clkcsr clock supplied by the system. figure 5-7 clock domains and reset all clock signals are independent and can be asynchronous one to another. if needed, the clkcsr and clkdma clock domains can be connected together with the same system clock signal in the user's system to consolidate global clock resources, or they can be from independent clock sources. a minimum frequency of clock clkcsr is required for proper operation of the transmit, receive, and general-purpose timers. the minimum frequency for clkcsr must be at least the clkt frequency divided by 64. for proper operation of the receive timer, the clkcsr frequency must be at least the clkr frequency divided by 64. if the clock frequency conditions described above are not met, do not use transmit interrupt mitigation control, receive interrupt mitigation control, or the general-purpose timer. appropriate clocks shou ld be also supplied when the hardware reset operation is performed. reset control hardware reset core10100 contains a single input rstcsr signal. this si gnal is sampled in the rstc component by clock clkcsr. the rstc component generates an internal asynchronous reset for every clock domain in core10100. the internal reset is generated by the input rstcsr and software reset. the internal reset remains active until the circuitry of all clock domains is reset. the external reset signal must be active (high) for at le ast one period of clock clkcsr in the users design. the minimum recovery time for a software reset is two clkcsr periods plus one maximum clock period among clkdma, clkt, and clkr. software reset software reset can be performed by setting the csr0.0 (swr) bit. the software reset will reset all internal flip-flops. clkr clkt clkdma tfifo rfifo tlsm rlsm dma tc bd rc csr clkcsr rstc
interface timing core10100 v4.0 70 v4.0 timing constraints actel recommends that correct timing constraints be used for the synthesis and layout stages of the design process. in particular, the cross-clock-domain pa ths must be constrained as follows: ? from "clkdma" to "clkt" uses clock period of clkdma ? from "clkt" to "clkdma" uses clock period of clkt ? from "clkdma" to "clkr" uses clock period of clkdma ? from "clkr" to "clkdma" uses clock period of clkr ? from "clkcsr" to "clkt" uses clock period of clkcsr ? from "clkt" to "clkcsr" uses clock period of clkt ? from "clkcsr" to "clkr" uses clock period of clkcsr ? from "clkr" to "clkcsr" uses clock period of clkr note: for core10100_ahbapb, clkdma should be re placed by hclk and clkscr by pclk.
v4.0 71 6 testbench operation and modification user testbench (core10100) an example user testbench is included with the obfuscated and rtl releases of core10100. the obfuscated and rtl releases provide the precompiled model sim model, as well as the source code for the user testbench, to ease the process of integrating the core10100 macro into a design and verify ing it. a block diagram of the example user design and testbench is shown in figure 6-1 . figure 6-1 core10100 user testbench the user testbench includes a simple example design that se rves as a reference for users who want to implement their own designs. rtl source code for the user testbench shown in figure 6-1 is included in the source directory for the obfuscated and rtl releases of core10100. the testbench for the example user design implements a subset of the functionality tested in the verification testbench, described in the previous chapte r. conceptually, as shown in figure 6-1 , two instantiations of the core10100 core are connected via simulated connections in the user testbenc h. example transmit and receive between the two core10100 units is demonstrated by the user testbench so you can gain a basic understanding of how to use the core. the source code for the user testbench contains the same example wrapper, chipmac, used in the verification testbench. for details on the support routines (tasks for verilog testbenches; functions and procedures for vhdl testbenches), see appendix a: user testbench support routines on page 75 . the user testbench consists of two cores: umac1 and umac2. in the example, umac1 transmits a 64-byte frame to umac2. to do so, the user testbench exercises the following steps: for umac1: 1. write several csr registers to set up the operation mode. 2. write two transmit descriptors into shared ram (uram1). 3. write the 64-byte data into shared ram (uram1). th e data consists of a sequence: 0, 1, 2, , 63. 4. turn on transmission. 5. wait for the transmit interrupt. 6. read the status register csr5. 7. clear the interrupt flags. core10100 user testbench simulated connection behavioral controller behavioral controller shared ram csr and dma interface chipmac shared ram umac1:chipmac mii csr and dma interface chipmac mii umac2:chipmac
testbench operation and modification core10100 v4.0 72 v4.0 for umac2: 1. write several csr registers to set up the operation mode. 2. write two receive descriptors into shared ram (uram2). 3. turn on receiving. 4. wait for the receive interrupt. 5. read the status register csr5. 6. check received data to match data sent by umac1. 7. clear the interrupt flags. the operations of umac1 and umac2 are concurrent. ahbapb user testbench (core10100_ahbapb) an example ahbapb user testbench to exercise the ah b and apb interfaces on core10100_ahbapb is included with the obfuscated and rtl releases of core10100. the obfuscated and rtl releases provide the precompiled model sim model, as well as the source code for the user testbench, to ease the process of integrating the core10100 macro into a design and verifying it. a block diagram of the example user design and testbench is shown in figure 6-2 . figure 6-2 core10100_ahbapb user testbench the testbench for the example user design implements the same test sequence as performed by the user testbench for core10100. the difference is that the behavioral processor accesses memory via the ahb and accesses the core via the apb. core10100 ahbapb simulated connection ahb bus behavioural controller memory apb bus core10100 ahbapb
v4.0 73 7 system operation this chapter provides various hints to ease the process of implementation and integration of core10100 into your own design. usage with cortex?-m1 core10100 can also be used wi th cortex-m1, the actel soft ip version of the popular arm? microprocessor that has been optimized for actel fpga devices. to create a design using cortex-m1 and core10100 ( figure 7-1 on page 73 ), you should use smartdesign. figure 7-1 example system using coremp7 and core10100

v4.0 75 a user testbench support routines the verification and user testbenches for the core10100 macro make use of various support routines, both in vhdl and verilog. the various support routines are described in this appendix for the vhdl and verilog testbenches. vhdl support the vhdl support routines (procedures and functions) ar e provided within a package. the support routines are referenced from within the user testbenches, via library and use clauses. procedure definitions procedure print(arguments) several print procedures are defined by overloading different argument types from string, integer, std_logic, and std_logic_vector. procedure print_wt(arguments) several print_wt procedures display information as the print procedure, but simulation time is added at the beginning of each display. procedure print_tx_descriptor the procedure print_tx_descriptor displays detailed information about a tr ansmit descriptor. it is defined below: procedure print_tx_descriptor ( marks : in string; des0 : in integer; des1 : in integer; des2 : in integer; des3 : in integer ) ; the string marks is displayed at beginning of the information, and des0, des1,des2 , and des3 are the four 32-bit words of the transmit descriptor. procedure print_rx_descriptor the procedure print_rx_descriptor displays detailed information about a receive descriptor. it is defined below: procedure print_rx_descriptor ( marks : in string; des0 : in integer; des1 : in integer; des2 : in integer; des3 : in integer ) ; the string marks is displayed at beginning of the information, and des0, des1,des2 , and des3 are the four 32-bit words of the receive descriptor.
user testbench support routines core10100 v4.0 76 v4.0 procedure print_csr5 the procedure print_csr5 displays detailed information on the cs r status register. it is defined below: procedure print_csr5 ( marks : in string; csr : in integer ); the string marks is displayed at beginning of the information, and csr is the value of csr register csr5. procedure write_csr the procedure write_csr writes a csr register. it is defined below: procedure write_csr ( signal clk : in std_logic; signal csrreq : out std_logic; signal csrrw : out std_logic; signal csrbe : out std_logic_vector(csrwidth/8-1 downto 0); signal csraddr : out std_logic_vector(csrdepth-1 downto 0); signal csrdatai: out std_logic_vector(csrwidth-1 downto 0); signal csrack : in std_logic; wa : in integer; wd : in integer ) the clkcsr is clk . the value of the csr register address is wa , and the value of the csr register is wd . procedure read_csr the procedure read_csr reads a csr register. it is defined below: procedure read_csr ( signal clk : in std_logic; signal csrreq : out std_logic; signal csrrw : out std_logic; signal csrbe : out std_logic_vector(csrwidth/8-1 downto 0); signal csraddr : out std_logic_vector(csrdepth-1 downto 0); signal csrdatai: out std_logic_vector(csrwidth-1 downto 0); signal csrack : in std_logic; ra : in integer; rd : out integer ) the clkcsr is clk . the value of the csr register address is ra, and the value of the csr register is rd .
core10100 v4.0 vhdl support v4.0 77 procedure tb_write_data the procedure tb_write_data writes data into shared ram, issued from the testbench. it is defined below: procedure tb_write_data ( count : in integer; signal clk : in std_logic; signal we : out std_logic; signal waddr : out std_logic_vector(datadepth-1 downto 0); signal wdata : out std_logic_vector(datawidth-1 downto 0); wa : in integer; wd : in int_array ) the clkdma is clk, count is number of the byte, wa is the beginning address of the sequence data, wd is an array storing the written data, we is the write enable issued from testbench, waddr is the write address to shared ram issued from the testbench, and wdata is the write data bus issued from the testbench. procedure tb_read_data the procedure tb_read_data reads data from shared ram, issued from the testbench. it is defined below: procedure tb_read_data ( count : in integer; signal clk : in std_logic; signal re : out std_logic; signal raddr : out std_logic_vector(datadepth-1 downto 0); signal rdata : out std_logic_vector(datawidth-1 downto 0); ra : in integer; rd : out int_array ) the clkdma is clk, count is the number of bytes, ra is the beginning address of the sequence data, rd is an array storing the written data, re is the read enable issued from testbench, raddr is the read address to shared ram issued from the testbench, and rdata is the read data to the testbench.
user testbench support routines core10100 v4.0 78 v4.0 procedure tb_write_tx_descriptor the procedure tb_write_tx_descriptor writes a transmit descriptor into shared ram, issued from the testbench. it is defined below: procedure tb_write_tx_descriptor ( marks : in string; signal clk : in std_logic; signal we : out std_logic; signal waddr : out std_logic_vector(datadepth-1 downto 0); signal wdata : out std_logic_vector(datawidth-1 downto 0); desaddr : in integer; des0 : in integer; des1 : in integer; des2 : in integer; des3 : in integer ) the string marks is displayed at beginning of the information, clk is the clkdma, desaddr is the beginning address of the descriptor, we is the write enable issued from the testbench, waddr is the write address to shared ram issued from the testbench, wdata is the write data bus issued from the testbench, and des0, des1,des2, and des3 are the four 32-bit words of the descriptor. procedure tb_write_rx_descriptor the procedure tb_write_rx_descriptor writes a receive descriptor into shared ram, issued from the testbench. it is defined below: procedure tb_write_rx_descriptor ( marks : in string; signal clk : in std_logic; signal we : out std_logic; signal waddr : out std_logic_vector(datadepth-1 downto 0); signal wdata : out std_logic_vector(datawidth-1 downto 0); desaddr : in integer; des0 : in integer; des1 : in integer; des2 : in integer; des3 : in integer ) the string marks is displayed at beginning of the information, clk is the clkdma, desaddr is the beginning address of the descriptor, we is the write enable issued from the testbench, waddr is the write address to shared ram issued from the testbench, wdata is the write data bus issued from the testbench, and des0, des1,des2, and des3 are the four 32-bit words of the descriptor.
core10100 v4.0 vhdl support v4.0 79 procedure tb_read_descriptor the procedure tb_read_descriptor reads a receive descriptor into shared ram, issued from the testbench. it is defined below: procedure tb__descriptor ( signal clk : in std_logic; signal re : out std_logic; signal raddr : out std_logic_vector(datadepth-1 downto 0); signal rdata : out std_logic_vector(datawidth-1 downto 0); desaddr : in integer; des0 : out integer; des1 : out integer; des2 : out integer; des3 : out integer ) the string marks is displayed at beginning of the information, clk is the clkdma, desaddr is the beginning address of the descriptor, re is the read enable issued from the testbench, raddr is the read address to shared ram issued from the testbench, rdata is the read data to the testbench, and des0, des1, des2, and des3 are the four 32-bit words of the descriptor. procedure tb_read_check_descriptor the procedure tb_read_check_descriptor reads a receive descriptor from shared ram, issued from the testbench and checked it against sequential data starting from 0 and incrementing with a step size of 1. it is defined below: procedure tb_read_check_rx_data ( count : in integer; signal clk : in std_logic; signal re : out std_logic; signal raddr : out std_logic_vector(shramdepth-1 downto 0); signal rdata : in std_logic_vector(shramwidth-1 downto 0); ra : in integer; signal error : inout integer ) the clkdma is clk, desaddr is the beginning address of descriptor, re is the read enable issued from the testbench, raddr is the read address to shared ram issued from the testbench, rdata is the read data to the testbench, count is the number of bytes, ra is the read address, and error is the error counter, which is incremented by the total number of mismatches.
user testbench support routines core10100 v4.0 80 v4.0 verilog support the verilog versions of the testbenches make use of the foll owing tasks, which are included within the top-level module of the user testbenches. verilog tasks task definitions task print_tx_descriptor the task print_tx_descriptor displays detailed information on a tran smit descriptor. it is defined below: task print_tx_descriptor; input[stringsize-1:0] marks; input des0; integer des0; input des1; integer des1; input des2; integer des2; input des3; integer des3; the string marks is displayed at beginning of the information, and des0, des1, des2, and des3 are the four 32-bit words of the transmit descriptor. task print_rx_descriptor the task print_rx_descriptor displays detailed information on a receive descriptor. it is defined below: task print_rx_descriptor; input[stringsize-1:0] marks; input des0; integer des0; input des1; integer des1; input des2; integer des2; input des3; integer des3; the string marks is displayed at beginning of the information, and des0, des1, des2, and des3 are the four 32-bit words of the receive descriptor.
core10100 v4.0 verilog support v4.0 81 ta s k print_csr5 the task print_csr5 displays detailed information on the csr status register. it is defined below: task print_csr5; input [stringsize-1 : 0] marks; input csr; integer csr; the string marks is displayed at beginning of the information, and csr is the value of csr register csr5. ta s k u1_write_csr the task u1_write_csr writes a csr register of mac unit 1. it is defined below: task u1_write_csr; input wa; integer wa; input wd; integer wd; the variable wa is the value of the csr register address, and wd is the value of the csr register. ta s k u2_write_csr the task u2_rite_csr writes a csr register of mac unit 2. it is defined below: task u2_write_csr; input wa; integer wa; input wd; integer wd; the variable wa is the value of the csr register address, and wd is the value of the csr register. ta s k u1_read_csr the task u1_ r ead_csr reads a csr register in mac unit 1. it is defined below: task u1_read_csr; input ra; integer ra; output rd; integer rd; the variable ra is the value of the csr register address, and rd is the value of the csr register. ta s k u2_read_csr the task u2_ r ead_csr reads a csr register in mac unit 2. it is defined below: task u2_read_csr; input ra; integer ra; output rd; integer rd; the variable ra is the value of the csr register address, and rd is the value of the csr register. ta s k u1_write_data the task u1_write_data writes data into shared ram unit 1, issued from the testbench. it is defined below:
user testbench support routines core10100 v4.0 82 v4.0 task u1_write_data; input count; integer count; input wa; integer wa; input[max_data_array_size-1:0] wd; the variable count is number of bytes, wa is the beginning address of the sequence data, and wd is an array storing the written data. ta s k u2_write_data the task u2_write_data writes data into shared ram unit 2, issued from the testbench. it is defined below: task u2_write_data; input count; integer count; input wa; integer wa; input[max_data_array_size-1:0] wd; the variable count is number of bytes, wa is the beginning address of the sequence data, and wd is an array storing the written data. ta s k u1_read_data the task u1_read_data reads data from shared ram unit 1, issued from the testbench. it is defined below: task u1_read_data; input count; integer count; input ra; integer ra; input[max_data_array_size-1:0] rd; the variable ra is the beginning address of the sequence data, rd is an array storing the written data, and re is the read enable issued from the testbench. ta s k u2_read_data the task u2_read_data reads data from shared ram unit 2, issued from the testbench. it is defined below: task u2_read_data; input count; integer count; input ra; integer ra; input[max_data_array_size-1:0] rd; the variable ra is the beginning address of the sequence data, rd is an array storing the written data, and re is the read enable issued from the testbench. ta s k u1_write_tx_descriptor the task u1_write_tx_descriptor writes a transmit descriptor into shared ram unit 1, issued from the testbench. it is defined below: task u1_write_tx_descriptor;
core10100 v4.0 verilog support v4.0 83 input [stringsize-1 : 0] marks; input desaddr; integer desaddr; input des0; integer des0; input des1; integer des1; input des2; integer des2; input des3; integer des3; the string marks is displayed at the beginnin g of the information, and des0, des1, des2, and des3 are the four 32-bit words of the transmit descriptor. ta s k u2_write_tx_descriptor the task u2_write_tx_descriptor writes a transmit descriptor into shared ram unit 2, issued from the testbench. it is defined below: task u2_write_tx_descriptor; input [stringsize-1 : 0] marks; input desaddr; integer desaddr; input des0; integer des0; input des1; integer des1; input des2; integer des2; input des3; integer des3; the string marks is displayed at the beginning of the information, desaddr is the starting address of the descriptor, and des0, des1, des2, and des3 are the four 32-bit words of the transmit descriptor.
user testbench support routines core10100 v4.0 84 v4.0 ta s k u1_write_rx_descriptor the task u1_write_rx_descriptor writes a receive descriptor into shared ram unit 1, issued from the testbench. it is defined below: task u1_write_rx_descriptor; input [stringsize-1 : 0] marks; input desaddr; integer desaddr; input des0; integer des0; input des1; integer des1; input des2; integer des2; input des3; integer des3; the string marks is displayed at the beginning of the information, desaddr is the starting address of the descriptor, and des0, des1, des2, and des3 are the four 32-bit words of the receive descriptor. ta s k u2_write_rx_descriptor the task u2_write_rx_descriptor writes a receive descriptor into shared ram unit 2, issued from the testbench. it is defined below: task u2_write_rx_descriptor; input [stringsize-1 : 0] marks; input desaddr; integer desaddr; input des0; integer des0; input des1; integer des1; input des2; integer des2; input des3; integer des3; the string marks is displayed at the beginning of the information, desaddr is the starting address of the descriptor, and des0, des1 , des2 , and des3 are the four 32-bit words of the receive descriptor.
core10100 v4.0 verilog support v4.0 85 ta s k u1_read_rx_descriptor the task u1_read_rx_descriptor reads a receive descriptor from shared ram unit 1, issued from the testbench. it is defined below: task u1_read_rx_descriptor; input [stringsize-1 : 0] marks; input desaddr; integer desaddr; output des0; integer des0; output des1; integer des1; output des2; integer des2; output des3; integer des3; the string marks is displayed at the beginning of the information , desaddr is the starting address of the descriptor, and des0, des1, des2, and des3 are the four 32-bit words of the descriptor. ta s k u2_read_rx_descriptor the task u2_read_rx_descriptor reads a receive descriptor from shared ram unit 2, issued from the testbench. it is defined below: task u2_read_rx_descriptor; input [stringsize-1 : 0] marks; input desaddr; integer desaddr; output des0; integer des0; output des1; integer des1; output des2; integer des2; output des3; integer des3; the string marks is displayed at the beginning of the information , desaddr is the starting address of the descriptor, and des0, des1, des2, and des3 are the four 32-bit words of the descriptor.
user testbench support routines core10100 v4.0 86 v4.0 ta s k u1_read_check_descriptor the task u1_read_check_descriptor reads a receive descriptor from shared ram unit 1, issued from the testbench and checked against a sequence of data starting from 0 and in crementing at a step size of 1. it is defined below: task u1_read_check_rx_data; input count; integer count; input ra; integer ra; the variable ra is the starting address, and count is the total number of bytes of the checked data. ta s k u2_read_check_descriptor the task u2_read_check_descriptor reads a receive descriptor from shared ram unit 2, issued from the testbench and checked against a sequence of data starting from 0 and in crementing at a step size of 1. it is defined below: task u2_read_check_rx_data ; input count ; integer count ; input ra ; integer ra ; the variable ra is the starting address, and count is the total number of bytes of the checked data.
v4.0 87 b transmit and receive functional timing examples transmit examples transmit overview a typical core10100 transmit is shown in figure b-1 . 1. host sends the transmit command and core10100 enters the transmit process. 2. core10100 starts to request the descriptors. 3. core10100 starts to request frame data and write them into the transmit fifo. 4. core10100 starts to transmit a frame on the mii interface. a typical transmit underg oes these four processes. in this chapter, more detailed dataflow diagrams are provid ed to illustrate the timing information for the above four processes. figure b-1 a typical transmit dataflow tps datareq datarw dataaddr twe twaddr twdata traddr trdata tx_en txd ffffffff xxxxxxxx f (1) (2) (3) (4)
transmit and receive functional timing examples core10100 v4.0 88 v4.0 core10100 enters transmit process the block csr performs this operation . 1. host sets the csr register csr6.13 st to start transmit. 2. the tps signal goes low after one clkcsr cycle, which indicates that core10100 enters the transmit process. figure b-2 enters transmit process core10100 starts to request transmit descriptors figure b-3 illustrates operations between tps goin g low and a transmit descriptor start. 1. host sends the transmit start command. 2. core10100 starts to fetch the first descriptor. note: t0 = 4 clkdma period + 3 clkcsr period + z. where z is 2 clkdma period if clkdma period is greater than clkcsr period, or z is 2 clkcsr period if clkcsr period is greater than clkdma period. delay z is the result of handshaking between csr clock domain and other domains in the design. figure b-3 core10100 starts transmit descriptor requests csrack csrbe[3:0] csrdatai[31:0] csraddr[7:0] clkcsr tps csrreq csrrw csr6.13st 30 (1) (2) (1) (2) clkdma clkcsr tps dataack datareq datarw dataeob datai[31:0] dataaddr[31:0] datao[31:0] 80000000 600007ff ffffffff 00003004 40000200 (1) (2) t 0
core10100 v4.0 transmit examples v4.0 89 transmit descriptor and data fetches transmit descriptor fetch in 32-bit mode 1. read the first 32-bit word of transmit descriptor. 2. read the second 32-bit word of transmit descriptor. 3. read the third 32-bit word of transmit descriptor. 4. read the first 32-bit data fetch and write into transmit fifo. 5. read the second 32-bit data fetch and write into transmit fifo. figure b-4 transmit descriptor fetch in 32-bit mode note: an extra cycle is inserted between any two descriptor fetches. transmit descriptor and da ta fetch in 16-bit mode 1. read the first 16-bit word of transmit descriptor. 2. read the second 16-bit word of transmit descriptor. 3. read the third 16-bit word of transmit descriptor. 4. read the fourth 16-bit word of transmit descriptor. 5. read the fifth 16-bit word of transmit descriptor. 6. read the sixth 16-bit word of transmit descriptor. 7. read the first 16-bit data fetch and write into transmit fifo. 8. read the second 16-bit data fetch and write into transmit fifo. 9. read the third 16-bit data fetch and write into transmit fifo. 10. read the fourth 16-bit data fetch and write into transmit fifo. clkdma clkt dataack datareq datarw datai[31:0] dataaddr[31:0] twe twaddr[8:0] twdata[31:0] traddr[8:0] trdata[31:0] tx_en txd[3:0] 80000000 600007ff 00000000 ffffffff 00003004 00003008 000 00000000 000 xxxxxxxx f (1) (2) (3) (4) (5)
transmit and receive functional timing examples core10100 v4.0 90 v4.0 figure b-5 transmit descriptor fetch in 16-bit mode transmit descriptor and da ta fetch in 8-bit mode 1. four reads of the first to fourth 8-bit words of the transmit descriptor. 2. four reads of the fifth to eighth 8-bit words of the transmit descriptor. 3. four reads of the ninth to twelfth 8-bit words of the transmit descriptor. 4. read the first 8-bit data fetch and write into the transmit fifo. 5. read the second 8-bit data fetch and write into the transmit fifo. 6. read the third 8-bit data fetch and write into the transmit fifo. 7. read the fourth 8-bit data fetch and write into the transmit fifo. figure b-6 transmit descri ptor fetch in 8-bit mode clkdma dataack datareq datarw dataeob datai[15:0] dataaddr[31:0] twe twaddr[9:0] twdata[15:0] 0000 07ff 0000 ffff ffff 000 0000 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) clkdma dataack datareq datarw dataeob datai[7:0] dataaddr[31:0] twe twaddr[10:0] 00 ff 00 000 (1) (2) (3) (4) (5) (6) (7)
core10100 v4.0 transmit examples v4.0 91 core10100 starts to transmit on mii 1. core10100 starts to write to the transmit data ram. 2. core10100 reaches the transmit fifo level (see table 4-11 on page 30 ). figure b-7 on page 91 shows that the transmit fifo threshold is set at 64 bytes, with sixteen 32-bit word writes. 3. transmit starts on mii. note: t0 = clkdma period fifo threshold level / datawidth 8 or t0 = clkdma period frame size / datawidth 8 in store and forward mode, and t1 = 3 clkdma period + 5 clkt period. figure b-7 transmit fifo thresh old and start of transmit on mii transmit on mii 1. core10100 starts to transmit the preamble and sfd. 2. core10100 sends the read address to the external transmit data ram. 3. core10100 reads the first 32 bits of data. 4. core10100 starts to transmit the data figure b-8 transmit on mii clkdma clkt twe twdata[31:0] twaddr[8:0] traddr[8:0] trdata[31:0] tx_en txd[3:0] 0000 00 00 000 000 00000000 f 1. 2. 3. t 0 t 1 clkt traddr[8:0] trdata[31:0] tx_en txd[3:0] 000 001 002 00 3 00000000 00000004 00000008 500 (1) (4) (3) (2) f
transmit and receive functional timing examples core10100 v4.0 92 v4.0 transmit on mii with 32-bit transmit data ram (1), (2) core10100 sends out requested read addresses. t0 is eight cycles. (3), (4) t1 is the time between core10100 sending out a read address request and the appearance of the requested data on mii. figure b-9 transmit on mii with 32-bit transmit data ram transmit on mii with 16-bit transmit data ram (1), (2) core10100 sends out requested read addresses. t0 is four cycles. (3), (4) t1 is the time between core10100 sending out a read address request and the appearance of the requested data on mii. figure b-10 transmit on mii wi th 16-bit transmit data ram transmit on mii with 8-bit transmit data ram (1), (2) core10100 sends out requested read addresses. t0 is two cycles. (3), (4) t1 is the time between core10100 sending out a read address request and the appearance of the requested data on mii. figure b-11 transmit on mii with 8-bit transmit data ram (1) (2) (3) (4) clkt tx_en traddr[8:0] trdata[31:0] txd[3:0] 001 002 003 004 504080c 00000004 00000008 0000000c 00000010 t 0 t 1 (1) (3) (4) (2) clkt tx_en traddr[9:0] trdata[15:0] txd[3:0] 000 001 002 003 004 0000 0004 0000 0008 5d040 t 0 t 1 clkt traddr[10:0] trdata[7:0] tx_en txd[3:0] 001 002 003 004 005 006 00 04 5 d 04 (1) (2) (4) (3) t 0 t 1
core10100 v4.0 receive examples v4.0 93 receive examples receive dataflow overview core10100 receives ethernet data from the mii interface, and the receive controller writes the received data into the receive data ram. the rfifo controller for core10100 starts to transfer received data from the receive data ram to the shared memory via the dma unit when the data in the receive data ram exceeds 64 bytes. figure b-12 on page 93 illustrates the received data travelling through differ ent core10100 interfaces. a typical receive consists of the following steps (as shown in figure b-12 on page 93 ): 1. core10100 starts to receive the preamble and sfd. 2. core10100 starts to write the receive data to the receive data ram. 3. core10100 writes the 64th byte of the received data to the receive fifo. 4. core10100 starts to transfer received data from the received data ram to the shared ram. figure b-12 a typical receive example rx_dv rxd[3:0] rwe rwaddr[8:0] rraddr[8:0] datareq dataack dataaddr[31:0] 0 5 00000 00 000 00000 00 (1) (2) (3) (4)
transmit and receive functional timing examples core10100 v4.0 94 v4.0 core10100 receives and w rites receive data ram core10100 receives and writes 32-bit receive data ram 1. core10100 starts to receive the preamble. 2. core10100 starts to receive the packet. 3. core10100 starts to write the first 32-bit word into the receive fifo. 4. core10100 starts to write the second 32-bit word into the receive fifo. note: t0 = 16 clkr period, t1 = 8 clkr period. figure b-13 core10100 receives and writes receive data ram core10100 receives and writes 16-bit receive data ram 1. core10100 starts to receive the preamble. 2. core10100 starts to receive the packet. 3. core10100 starts to write the first 16-bit word into the receive fifo. 4. core10100 starts to write the second 16-bit word into the receive fifo. note: t0 = 16 clkr period, t1 = 4 clkr period figure b-14 core10100 receives and writes 16-bit receive data ram clkr rps rx_dv rxd[3:0] rwe rwaddr[8:0] 05 12 000 001 002 (1) (3) (2) (4) t 0 t 1 clkr rx_dv rwe rxd[3:0] rwaddr[9:0] rwdata[15:0] 050123456789 000 001 00 2 fff0 fff5 (1) (2) (3) (4) t 0 t 1
core10100 v4.0 receive examples v4.0 95 core10100 receives and writes 8-bit receive data ram 1. core10100 starts to receive the preamble. 2. core10100 starts to receive the packet. 3. core10100 starts to write the first 8-bit word into the receive fifo. 4. core10100 starts to write the second 8-bit word into the receive fifo. note: t0 = 16 clkr period, t1 = 2 clkr period. figure b-15 core10100 receives an d writes 8-bit receive data ram transfer receive data to shared memory 32-bit word transfer from receive data ram to shared memory 1. core10100 writes the 64th byte of the frame into the receive data ram. 2. core10100 starts to send the data request to transfer received data into the shared memory. 3. the first 32-bit word is written into the shared memory via the data interface. 4. the 64th byte of the frame is written into the shared memory. note: t0 = 6 clkdma period. figure b-16 32-bit word transfer from receive data ram to shared memory clkr rx_dv rwe rxd[3:0] rwaddr[10:0] rwdata[7:0] (1) (2) (3) (4) t 0 t 1 05 000 f0 f5 01 234 5678 (1) (2) (3) (4 ) t 0 clkdma clkr rwe rwaddr[8:0] rraddr[8:0] rrdata[31:0] dataack datareq dataaddr [31:0] datao[31:0] 00e 00f 010 000 76543210 00001014 76543210 0
transmit and receive functional timing examples core10100 v4.0 96 v4.0 16-bit word transfer from receive data ram to shared memory 1. core10100 writes the 64th byte of the frame into the receive data ram. 2. core10100 starts to send the data request to transfer received data into the shared memory. 3. the first 32-bit word is written into the shared memory via the data interface. 4. the 64th byte of the frame is written into the shared memory. figure b-17 16-bit word transfer from receive data ram to shared memory 8-bit word transfer from receive data ram to shared memory figure b-18 8-bit word transfer from receive data ram to shared memory core10100 receive descriptor fetch the receive descriptor fetch timing is essentially the same as the transmit descriptor fetch timing. in reality, transmit descriptor fetches and receive descriptor fetches can happen mixed or alternately through the dma interface. refer to figure b-4 on page 89 , figure b-5 on page 90 , and figure b-6 on page 90 . clkdma clkr rwe rraddr[9:0] rwaddr[9:0] rrdata[15:0] dataack datareq datarw dataaddr[31:0] datao[15:0] (1) (2) (3) 000 0 0 03f 040 041 042 0000 00001014 0000 clkdma clkr rwe rwaddr[10:0] rraddr[10:0] rrdata[7:0] dataack datareq dataaddr[31:0] datao[7:0] (1) (2) (3) 03e 03f 040 041 042 043 044 0 000 00 00001014 00
v4.0 97 c list of document changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v4.0) page v3.1 the core name core10/100 was changed to core10100, and core10/100-ahb was changed to core10100_ahb. the core version was changed from v3.2 to v4.0. n/a figure 1 core10100 block diagram and figure 2 typical core10100 application were updated to change mii to rmii/mii. 5 figure 3 arm-based system using core10100_ahbapb was replaced. 6 instances of coreconsole were changed to smartdesign throughout the document. n/a table 1 core10100 device utilization and performance for an 8-bit datapath through table 6 core10100_ahbapb device utilization and performance for a 32-bit datapath were updated. 7 C 8 table 7 parameter settings was revised to update the tfifodepth and rfifodepth values. a row was added for rmii. the datadepth parameter valu e was changed to 20 for the 8-bit cores. 10 figure 1-1 core 10100 architecture and figure 1-2 core10100_ahbapb architecture were revised to add an mii to rmii block. 11 C 12 the csr C control/status register logic section was revised to remove reference to the power management functionality of core10100. 13 the licensing section was revised to remove the evaluation version. the coreconsole section was removed. figure 2-1 core10100 configuration within smartdesign and figure 2-2 core10100_ahbapb configuration within smartdesign replaced previous figures of co nfiguration in coreconsole. the importing into libero ide section and simulation flows section were updated. the synthesis in libero ide section is new. 15 C 18 the introduction to the interface descriptions section was revised to list interfaces as csr and amba instead of legacy, ahb, and apb. 19 proasic3l was added to the values for the family parameter in table 3-1 core10100 parameters . a default value column was added. the acceptable values were revised for the following parameters: datadepth, tcdepth, rcdepth, tfifodepth, and rfifodepth. the description was revised for tcdepth and rcdepth. 19 a default value column was added to table 3-2 core10100_ahbapb parameters . acceptable values were revised for the following parameters: ahb_awidth, tcdepth, rcdepth, tfifodepth, and rfifodepth. the description was revised for tcdepth and rcdepth. 20 the section title legacy interface signals was changed to csr interface signals . table 3-3 core10100 signals and table 3-4 signals included in core10100 and core10100_ahbapb were revised to change signal names to all capital letters. the subheadi ng mii phy interface in table 3-4 was revised and is now rmii/mii phy interface. three signal names changed: rxer to rx_er, rxdv to rx_dv, an d txen to tx_en. the descriptions were revised to include rmii for rmii_clk and crs_dv. the descriptions for clkt, clkr, rx_er, rxd,txd, and rmii_clk were revised in table 3-4 signals included in core10100 and core10100_ahbapb . table 3-5 core10100_ahbapb signals was moved to the end of the chapter. 22 C 24 the reset value for csr9 was changed to fff483ffh in table 4-1 csr l ocations . 27 the permissible values were changed for pbl in table 4-3 bus mode register bit functions . 1 and 2 are no longer permissible values. 28
98 v4.0 list of document changes core10100 v4.0 v3.1 (contd) the function for ttm was revised to add information about rmii mode in table 4-16 operation mode register bit functions . 33 in table 4-23 mii management and serial rom interface register (csr9) , mii was changed to mden. 38 the title of figure 4-1 i/o tristate buffer connections was changed from external tristate buffer connections. 39 the function for con was revised to add information about when the bit should be written in table 4-26 general-purpose timer and interrupt mitigation control bit functions . 40 the description for rx_er was revised in table 4-40 external phy interface signals . 57 the mii to rmii interface section was revised to state the internal clock net clk_tx_rx must be assigned to a global clock network. the clk_tx_rx was added to figure 4-16 mii_to_rmii internal architecture . 64 figure 5-6 simple transfer is new. 68 the core10100-rmii interface section is new. 68 the verification testbench section was removed. referenc es to the evaluation release of core10100 were removed from the testbench operation and modification section . 71 the usage with cortex?-m1 section replaced the usage with coremp7 section. 73 the software drivers chapter of the handbook was deleted. it contained only the following text: example software drivers are available from actel for core 10100. contact actel technical support for information ( tech@actel.com ). n/a the verification tests description appendix was removed. n/a v3.0 all references to the core100100 datasheet were removed, as it has been superseded by the core10100 handbook. n/a v2.3 the memory blocks section was updated to add information on the mii and rmii. 14 the rmii parameter was added to table 3-1 core10100 parameters and table 3-2 core10100_ahbapb parameters . 19 , 20 the rmii_clk and crs_dv signals were added to table 3-4 signals included in core10100 and core10100_ahbapb . 24 the descriptions for csr6.13 and csr6.1 were updated in table 4-16 operation mode register bit functions . 33 the description for csr8.(15..0) was updated in table 4-22 missed frames and overflow counter bit functions . 38 a new sentence was added to the end of the mac address and setup frames section regarding setup frame buffer size. 49 the first three rows of table 4-38 perfect filtering setup frame buffer were revised. 50 the sentence, before writing to csr4, the mac must be in a stopped state was added to the transmit process section . the sentence, before writing to csr3, the mac must be in a stopped state was added to the receive process section . a sentence was also added to clarify when the receive state machine goes into a stopped state. 52 , 54 the following sentence was added to the receive address filtering section : to receive the broadcast frame, the hash table bit corresponding to the broadcast address crc value should be set. 62 the steps for calculating crc with hash filtering section is new. 63 the mii to rmii interface section is new. 64 v2.2 the supported device families section was added and the memory requirements section was updated to include proasic3l. 7 , 10 previous version changes in current version (v4.0) page
core10100 v4.0 v4.0 99 v2.1 core version changed from v3.1 to v3.2. 7 the rc C receive controller section was updated to remove the words using an external address ram from the sentence about internal address filtering. 14 table 3-1 core10100 parameters and table 3-2 core10100_ahbapb parameters were updated for the addrfilter description. 19 , 20 in table 4-1 csr l ocations , the reset value for csr9 was updated. a table note was added. 27 a paragraph was added to the function description for the csr0.0 bit in table 4-3 . 28 table 4-23 mii management and ser ial rom interface register (csr9) was updated to add one column. 38 table 4-24 mii management and se rial rom register bit functions was updated to change the symbol for bit csr9.18 to mden. an explanatory sentence was added to the function. 38 figure 4-1 i/o tristate buffer connections and the text preceding it were update d to indicate an active low enable with the tristate buffer. 39 the receive address filtering section was updated to add a sentence at the end describing how to enable the functionality discussed. 62 v2.0 added version number to cover page. title added the core versions section. 7 added the igloo/e family to table 1 , table 2 , table 3 , table 4 , table 5 , and table 6 . 7 C 9 added the igloo/e family to the memory requirements section. 10 changed the reset value for csr1 and csr2 in table 4-1 . 27 changed the left-hand column of table 4-27 to rdes0C3. 43 changed the left-hand column of table 4-32 to tdes0C3. 46 changed the datar signal to datarw in figure 5-2 and figure 5-3 . 66 previous version changes in current version (v4.0) page

v4.0 101 d product support actel backs its products with various support services including customer service, a customer technical support center, a web site, an ftp site, electronic mail, and worldw ide sales offices. this append ix contains info rmation about contacting actel and usin g these support services. customer service contact customer service for non-technical product support , such as product pricing, product upgrades, update information, order status, and authorization. from northeast and north central u.s.a., call 650.318.4480 from southeast and southwest u.s.a., call 650. 318.4480 from south central u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 actel customer technical support center actel staffs its customer technical support center with highly skilled engineers who can help answer your hardware, software, and design questions. the custo mer technical support center spends a gr eat deal of time creating application notes and answers to faqs. so, before you contact us, please visi t our online resources. it is very likely we have already answered your questions. actel technical support visit the actel customer support website ( www.actel.com/custsup/search.html ) for more information and support. many answers available on the searchable web resource includ e diagrams, illustrations, and links to other resources on the actel web site. website you can browse a variety of technical and non-technical information on actels home page , at www.actel.com . contacting the customer technical support center highly skilled engineers staff the technical support center from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. several ways of co ntacting the center follow: email you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design problems, you can email your design files to receive assistance. we constantly monitor the email account throughout the day. when sending your request to us, please be sure to include your full name, company name, and your contact information for effi cient processing of your request. the technical support email address is tech@actel.com .
product support core10100 v4.0 102 v4.0 phone our technical support center answers all calls. the center re trieves information, such as your name, company name, phone number and your question, and then issues a case number. the center then forwards the information to a queue where the first available application engineer receives the data and returns your call. the phone hours are from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. the technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outside the us time zones can either contact technical support via email ( tech@actel.com ) or contact a local sales office. sales office listings can be found at www.actel.com/contact/offices/index.html .
v4.0 103 a actel electronic mail 101 telephone 102 web-based technical support 101 website 101 addressing control and status registers 27 architecture 11 arm-based system 6 b bus mode register (csr0) 27 c clock controls 68 cock and reset control 68 collision detection 5 collision handling 60 contacting actel customer service 101 electronic mail 101 telephone 102 web-based technical support 101 core10100 block diagram 5 csr interface 65 data interface 65 core10100_ahbapb ahb interface 68 apb interface 67 crc calculate with hash filtering 63 csr 38 definitions 27 csr0 27 csr1 29 csr11 40 csr2 29 csr3 30 csr4 30 csr5 30 csr6 33 csr7 36 csr8 37 customer service 101 d deferring 61 descriptors 41 chained structure 43 overview 41 ring structure 42 transmit 46 device utilization 7 dma controller 51 f frame data 41 g general-purpose timer an d interrupt mitigation control register (csr11) 40 i interface signals ahb/apb 26 common 24 csr 22 interface types 19 internal operation 51 interrupt enable register (csr7) 36 interrupts controller 55 scheme 56 l libero ide synthesis 18 licenses obfuscated 15 rtl 15 types 15 m mac address 49 mac ethernet controller 5 memory requirements 10 mii interface 57 signals 57 mii management and serial rom interface register (csr9) 38 mii management interface 39 index
104 v4.0 index core10100 v4.0 mii to rmii interface 64 mii_to_rmii internal architecture 64 mii-to-rmii interface 68 missed frames and overflow counter register (csr8) 37 o operation mode register (csr6) 33 p parameters core10100 19 core10100_ahbapb 20 performance data 7 place-and-route in libero ide 18 primary blocks 5 product support 101 ? 102 customer service 101 electronic mail 101 technical support 101 telephone 102 website 101 r receive address filtering 62 receive descriptor list base address register (csr3) 30 receive poll demand register (csr2) 29 receive process 54 transitions 55 register maps 27 reset control 69 rmii interface 68 s setup frames 49 smartdesign 7 core10100 configuration 16 core10100_ahbapb configuration 17 status register (csr5) 30 supported interfaces 7 synthesis in libero ide 18 t technical support 101 timer, general-purpose 57 timing constraints 70 tool flows 15 transmit descriptor list base address register (csr4) 30 transmit poll demand register (csr1) 29 transmit process 52 transitions 53 typical application using core10100 5 w web-based technical support 101

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